Abstract: An apparatus and method for bi-directional format conversion and transfer of data between integer and floating point registers is provided. A floating point register is configured to store floating point data, and integer data, in a variety of numerical formats. Data is moved in and out of the floating point register as integer data, and is converted into floating point format as needed. Separate processor instructions are provided for format conversion and data transfer to allow conversion and transfer operations to be separated.

Abstract: An apparatus and method are provided for concurrently loading single-precision operands into registers in a microprocessor floating point register file. The apparatus includes translation logic, data logic, and write back logic. The translation logic receives a load macro instruction prescribing an address, and decodes the load macro instruction into a double load micro instruction. The double load micro instruction directs the microprocessor to retrieve the two single-precision operands from the address and to load the two single-precision operands into the two floating point registers. The data logic, coupled to the translation logic, executes the double load micro instruction and retrieves the two single-precision operands from the address. The write back logic, coupled to the data logic, loads the two single-precision operands into the two floating point registers during a single write cycle.

Abstract: An apparatus and method for improving microprocessor performance by improving the prediction accuracy of conditional branch instructions is provided. A static branch predictor makes a prediction of the outcome of a conditional branch instruction based on the branch test type and the branch target address displacement sign. A branch history table stores a bit indicating whether the prediction of the static predictor agreed with the outcome of the last execution of the branch instruction. If the history table bit agrees, then the static prediction is used. Otherwise, the opposite of the static prediction is used.

Abstract: An apparatus and method are provided for locally intercepting and servicing a long-distance call, prior to incurring charges associated with routing of the long-distance call over a corresponding long-distance carrier channel. A caller is immediately given the option to send a voicemail message to a recipient rather than completing the long-distance call. If the caller so chooses, the voicemail is recorded locally, the call is terminated, and the voicemail message is subsequently transmitted to the recipient via a data-centric network. The apparatus includes a telephony-centric network server and a message router. The telephony-centric network server detects initiation of the long-distance call, it intercepts the long-distance call, and it transmits the voicemail message over the data-centric network. The message router is coupled to the telephony-centric network server. The message router forwards the voicemail message over the data-centric network to a recipient.

Abstract: An apparatus and method are provided for executing a forward branch in a microprocessor. The apparatus has translation logic and instruction fetch logic. The translation logic utilizes a branch predictor to determine if a conditional branch should be taken or not. If the branch is predicted taken, then a branch accelerator in the instruction fetch logic determines if a branch target instruction has already been stored for translation in an instruction buffer by summing the length of the conditional branch instruction to a displacement provided by the conditional branch instruction. If the branch target instruction is already within the instruction buffer, contents of the instruction buffer are simply shifted by the number of bytes indicated by the sum to move the branch target instruction to the front of the buffer.

Abstract: An apparatus and method for improving the execution of conditional branch instructions is provided. A static branch predictor makes predictions about the outcomes of branch instructions based upon a combination of the test type (such as jump on overflow, jump if negative, jump if zero, jump on carry, etc.) and the sign of the displacement of the branch instruction. If the test type of the branch instruction is one of a subset of test types from which the branch outcome can accurately be predicted solely from the test type, then the predictor makes such a prediction. Otherwise, the predictor makes a prediction based upon the sign of the displacement used to calculate the branch target address. In this case, backward jumps are predicted taken and forward jumps are predicted not taken.

Abstract: An apparatus and method for performing single precision multiplication in a microprocessor are provided. The apparatus includes translation logic and extended precision floating point execution logic. The translation logic decodes a single precision multiply instruction into an associated micro instruction sequence directing the microprocessor to fetch a single precision operand from memory and convert it to extended precision format. In addition, the associated micro instruction sequence directs floating point execution logic employing a dual pass multiplication unit to skip a pass associated with computing an insignificant partial product. This insignificant partial product would otherwise result from multiplication of a multiplicand by zeros which are appended to the significand of the fetched operand when it is converted to extended precision format.

Abstract: A method for adaptively training a human subject to process, and to distinguish between, similar acoustic events that are common in spoken language is provided. The method utilizes sequences of up/down frequency sweeps, of varying frequency and duration, and having varying inter stimulus intervals (ISI) between the frequency sweeps. A sequence is presented to the subject for order identification. The subject must listen to the up/down order of a sequence, and signal identification of the up/down order according to what s/he heard. Signal identification is provided utilizing a computer display, a mouse, and graphical buttons corresponding to the up/down frequency sweeps. Correct order identification causes the process to adaptively reduce the ISI separating the frequency sweeps, to reduce the duration of the frequency sweeps, to alter the frequency of the frequency sweeps, and to increase the number of frequency sweeps within a sequence.

Abstract: An apparatus and method are provided for executing a push all/pop all instruction in a pipeline microprocessor. The apparatus includes an instruction buffer and a translator. The instruction buffer provides the push all/pop all instruction, directing the microprocessor to store/retrieve multiple operands to/from a stack. The translator generates a sequence of micro instructions to store/retrieve the multiple operands. Accesses to a pair of operands which are together aligned are combined into a single access.

Abstract: An apparatus and method for training of auditory and graphical discrimination in humans is provided. The method and apparatus provides a number of stimulus sets, each stimulus set having a target phoneme, and associated grapheme, and a number of distractor phonemes, and associated graphemes. Upon initiation of a trial, a target phoneme is presented to a subject. A stimulus stream is then prepared that consists of a random sequence of distractor phonemes. Located within the sequence of distractor phonemes is the target phoneme. The stimulus sequence is presented to the subject for identification of the target phoneme within the sequence. Speech processing is used to provide multiple levels of emphasis for enhancing a subject's ability to discriminate between similarly sounding phonemes. The processing is applied to the presentation of the target phoneme and the stimulus stream.

Abstract: An apparatus and method for improving microprocessor performance by improving the prediction accuracy of conditional branch instructions is provided. A dynamic branch predictor speculatively updates global branch history information based on the prediction of a first branch instruction so that the predictor can predict the outcome of a second branch instruction following closely in the pipeline with the benefit of the first prediction. This improves the prediction accuracy where the first branch has not been resolved prior to the time when the second prediction is ready to be made. If the first prediction turns out to be incorrect, the global branch history is restored from a previously saved copy and updated with the first branch instruction's actual outcome.

Abstract: An apparatus and method for calculating a square root of an operand in a microprocessor are provided. The microprocessor has a plurality of square root instructions, each of which specifies a square root calculation precision. The apparatus includes translation logic and execution logic. The translation logic decodes the square root macro instruction into a plurality of prescribed-precision machine instructions according to the square root calculation precision specified by the plurality of square root instructions. The execution logic, coupled to the translation logic, receives the plurality of prescribed-precision machine instructions and calculates the square root of the operand according to the specified square root calculation precision. At least one of the plurality of square root instructions specifies the square root calculation precision such that less significant bits are calculated in the square root than are provided in the operand.

Abstract: A microprocessor is provided having selective control features to determine its core-to-bus clock ratio. The microprocessor includes a fuse and buffer/control logic. The fuse, fabricated on the microprocessor's metalization or poly layer, can be blown with a laser during fabrication. When blown, the fuse provides a permanent state that prescribes a fixed core-to-bus clock ratio. The buffer/control logic is coupled to the fuse. The buffer/control logic accepts the permanent state and directs the microprocessor to set the core-to-bus clock ratio to a fix value, thus disabling control of the core-to-bus clock ratio via external clock ratio control signals.

Abstract: An apparatus and method for training the cognitive and memory systems in a subject is provided. The apparatus and method incorporates a number of different programs to be played by the subject. The programs artificially process selected portions of language elements, called phonemes, so they will be more easily distinguished by the subject, and gradually improves the subject's neurological processing and memory of the elements through repetitive stimulation. The programs continually monitor a subject's ability to distinguish the processed language elements, and adaptively configures the programs to challenge and reward the subject by altering the degree of processing. Through adaptive control and repetition of processed speech elements, and presentation of the speech elements in a creative fashion, a subject's cognitive processing of acoustic events common to speech, and memory of language constructs associated with speech elements are significantly improved.

Abstract: An apparatus and method for exchanging operands within a microprocessor is provided. The apparatus contains a translator for generating a micro instruction that loads a first operand into a second location, and a second operand into a first location without specifying intermediate storage of either operand. In addition, interlock control is provided to disable interlock delay when executing an exchange instruction. Disabling the interlock control allows an exchange operation to be performed in 2 or less clock cycles. Also, a register file is used that allows two operands to be written to it in parallel. Operand write control is used with the register file to switch the operand specifiers in an exchange instruction during write back, to allow the specifiers used to retrieve operands from the register file to also be used for the exchange.

Abstract: An apparatus and method for improving the execution of floating point instructions in a microprocessor is provided. During decode of a floating point instruction, translation logic generates absolute addresses of specified registers in a floating point register file. These absolute references, as opposed to relative references to a top-of-stack, are inserted into associated micro instructions. In the event of an exception, synchronization logic provides an architected top-of-stack for the floating point instruction associated with the exception to the translation logic so that subsequent instructions will properly reference floating point registers.

Abstract: An apparatus and method for prefetching data into a cache memory system is provided. A prefetch instruction includes a hint type that allows a programmer to designate whether, during a data retrieval operation, a hit in the cache is to be ignored or accepted. If accepted, the prefetch operation completes. If ignored, the prefetch operation retrieves data from the main memory, even though the cache believes it contains valid data at the requested memory location. Use of this invention in a multiple bus master processing environment provides the advantages of using a cache memory, i.e., burst reads and a relatively large storage space as compared to a register file, without incurring disadvantages associated with maintaining data coherency between the cache and main memory systems.

Abstract: An apparatus and method for improving the execution of conditional branch instructions is provided. A translator detects a conditional branch instruction during decode of the instruction, and provides a displacement to a target address calculator. The target address calculator calculates a target address for the branch instruction during decoding of the branch instruction by summing the displacement with a next instruction linear address. A signal is provided to indicate whether the target address is within a current code segment. The target address is provided to an instruction fetcher for use by the fetcher if it is predicted that the branch will be taken. Validation of the calculated target address is made by comparing the signal with the sign of the displacement.

Abstract: A method for improving the execution of significant bit scans on a data entity in a computer system is provided. The data entity is examined in a number of iterations equal to the base two logarithm of the size of the data entity in bits, N. Initially, half of the data entity is examined to determine if the significant bit is present. If not, the other half of the data entity is examined. The half within which the significant data entity resides is then iteratively halved and examined in each successive iteration of the method until the number of bits examined is equal to one.

Abstract: A method for burst transferring of data in a processing system is provided. The processing system has a data bus width of W bytes (W even) and a cache line length of L bytes (L even). The cache line has L/W banks, the lowermost bank being in an odd position and the uppermost bank being in an even position. In a request for a particular data entity, a series of addresses are issued on the address bus to fill the associated cache line. The first address is always for a particular cache bank to which the particular data entity is mapped. The remaining addresses are sequenced ascending linearly, modulo L. If the particular data entity is mapped to an even cache bank, but not to the uppermost cache bank, then L/W remaining addresses are issued, beginning with the base address of the cache bank immediately following the cache bank to which the particular data entity is mapped.