Abstract: An electronic device with automatic switching input interfaces and a switching method thereof. The electronic device supports an Advanced Configuration Power Interface (ACPI), and includes a display unit, a storage unit, a memory unit, and an embedded controller. The display unit can be changed to a first position or a second position, and sends a signal to an embedded control unit when the display unit is at different positions. A management program running in the electronic device queries the ACPI and the embedded control unit to check the position and state of the display unit, so as to automatically load and run a corresponding program of a virtual input interface or a physical input interface into the memory unit, and remove the other program from the memory unit at the same time.

Abstract: System and method for handling multiple connection requests between an Access Terminal (AT) and an Access Network (AN). The method may include receiving a first connection request. Connection request information regarding a number of connection requests may be updated based on receiving the first connection request. If there is not a currently active wireless connection, a connection may be established between the AT and the AN. If there is a currently active wireless connection, a notification may be sent indicating that the wireless connection between the AT and the AN has been established. A connection release request may be received. Accordingly, the update connection request information may be updated based on receiving the connection release request. If there is not a currently active wireless connection, the wireless connection between the AT and the AN may be closed.

Abstract: An electrostatic discharge guide using metal sputtering process and modifying plastic case is applied to an electronic device. The plastic case and a metal case are laminated. The plastic case is defined with a tip portion spaced from the metal case on side wall thereof. A conductive layer formed on the surface of the plastic case opposite to the metal case extends to the tip of the tip portion, and is electrically connected to a ground of the electronic device. Therefore, when electrostatic charges accumulated on the metal case exceed a specific value, the static electricity is discharged to the ground of the electronic device based on the point discharge principle, instead of causing an electric shock to a user.

Abstract: System and method for processing received packets. A QuickNak (QN) packet may be received. The QN packet may include a segmentation and reassembly (SAR) packet. The SAR packet may be delivered to a SAR receiver and it may be determined if there are missing packets, e.g., after delivery of the SAR packet. If there are missing packets, a QN indication may be generated and provided to the SAR receiver. Alternatively, the SAR receiver may receive the SAR packet with the QN indication. Accordingly, the SAR packet may be stored in a reception buffer or delivered to an upper layer, e.g., depending on current state variables. The SAR receiver may update the state variables and determine if there are missing packets. If there are missing packets, the SAR receiver may deliver an indication of the missing packets.

Abstract: A computer system includes compute nodes coupled through a switch to shared or non-shared I/O devices. The switch includes a pool of bridge headers and virtual bridges coupling a root port of a compute node to each of one or more shared or non-shared I/O devices. The switch is configured to associate each of the virtual bridges with a respective one of the fixed pool of bridge headers, receive a packet including data identifying the root port and a shared or non-shared I/O device, and route the packet in response to comparing data in the packet to data in the bridge headers associated with the virtual bridges. The virtual bridges comprise a hierarchy of virtual bridges in which one virtual bridge connects the root port to the remaining virtual bridges of the hierarchy. The switch may change the associations between virtual bridges and bridge headers.

Abstract: A network interface controller is provided which is shareable by a plurality of operating system domains (OSDs) within their load-store architecture. The controller includes local resources for corresponding to the OSDs, and global resources corresponding to both the OSDs and a network fabric. A method and apparatus is provided for distinguishing between the local and global resources, for purposes of reset and configuration. The controller allows a reset of only those local resources which are associated with the OSD transmitting the reset. Registration logic allows one of the OSDs to register as master, for configuration and reset of global resources.

Abstract: Provided are systems, methods and techniques that use an embedded error-detection code within a received communication signal to determine when to stop iterative decoding of the communication signal.

Abstract: An electronic device structure includes an upper case, a lower case, a main board, a suspending member, and a fixing member. The upper case and the lower case respectively have an upper combining column and a lower combining column. The main board has a through hole, the upper combining column passes through the through hole, and a size of the through hole is larger than a size of the upper combining column, such that a moving gap is kept between the upper combining column and the through hole. The suspending member is combined with a side of the main board and spaced with the main board by a suspending distance. The fixing member passes through the lower combining column and the suspending member and is fixed on the upper combining column, such that the main board is disposed on the lower combining column through the suspending member.

Abstract: System and method for developing cognitive skills in a student, utilizing a computing device to present stimuli and to record responses. A stimulus may be graphically presented to the student via the computing device, and the student may be required to respond to the stimulus. A determination may then be made as to the correctness of the student's response. The graphically presenting, requiring, and determining may be performed for each of a plurality of stimuli. Additionally, the graphically presenting, requiring, determining, and performing may be performed in an iterative manner to improve the cognitive skills of the student. Various exercises directed to different cognitive skills and learning approaches may utilize this basic framework, and may be performed in an iterative manner to build cognitive skills in the student.

Abstract: Spread spectrum clock generation (SSCG) using phase modulation. A first clock signal having a first frequency spectrum may be modulated using phase modulation to produce a second clock signal. The phase modulation may include providing a phase modulation profile corresponding to the integrated frequency modulation profile, to adjust a scaling factor used in obtaining the second clock signal. The phase modulation profile may be provided in the form of a pulse or pulses, which may be injected through pulse density modulation or pulse width modulation at the output of a phase frequency detector comprised in a phase locked loop circuit used in generating the second clock signal. This modified phase modulation technique removes the down spread limitation present in traditional PM implementations, and also provides better jitter performance and lower cost than traditional PM implementations.

Abstract: A method for correcting gain imbalance error, phase imbalance error and DC offset errors in a transmitter having an OFDM-based I/Q modulator is disclosed. The method employs a compensator prior to the I/Q-modulator to compensate for the gain and phase imbalance and DC offset. The compensator is efficiently updated with the estimated values of gain and phase imbalance and DC offsets obtained by performing the DFT operation in the digital baseband domain while sending a pair of orthogonal test tones to the modulator's inputs from a digital baseband chip, then down converting the RF modulated signal through a nonlinear device and a bandpass filter to a baseband signal, and finally sampling it using an A/D. The delay mismatch, which is mainly generated by lowpass filters between the I and Q branches, is also minimized in this method.

Abstract: A computer system includes compute nodes coupled through a switch to shared or non-shared I/O devices. The switch includes a pool of bridge headers and virtual bridges coupling a root port of a compute node to each of one or more shared or non-shared I/O devices. The switch is configured to associate each of the virtual bridges with a respective one of the fixed pool of bridge headers, receive a packet including data identifying the root port and a shared or non-shared I/O device, and route the packet in response to comparing data in the packet to data in the bridge headers associated with the virtual bridges. The virtual bridges comprise a hierarchy of virtual bridges in which one virtual bridge connects the root port to the remaining virtual bridges of the hierarchy. The switch may change the associations between virtual bridges and bridge headers.

Abstract: A system and method for computing A mod (2n?1), where A is an m bit quantity, where n is a positive integer, where m is greater than or equal to n. The quantity A may be partitioned into a plurality of sections, each being at most n bits long. The value A mod (2n?1) may be computed by adding the sections in mod(2n?1) fashion. This addition of the sections of A may be performed in a single clock cycle using an adder tree, or, sequentially in multiple clock cycles using a two-input adder circuit provided the output of the adder circuit is coupled to one of the two inputs. The computation A mod (2n?1) may be performed as a part of an interleaving/deinterleaving operation, or, as part of an encryption/decryption operation.

Abstract: A processor for a portable electronic device. The processor includes a RISC (reduced instruction set computing) core a CISC (complex instruction set computing) core, a video accelerator circuit and an audio accelerator circuit. Each of the video and audio accelerator circuits are coupled to both the RISC and CISC cores, with both cores and both accelerator circuit being incorporated into a single integrated circuit. In a first plurality of operational modes, the RISC core is active, while the CISC core is in one of a sleep state or a power off state. In a second plurality of modes, both the RISC and CISC cores are active.

Abstract: An apparatus and method is provided for allowing I/O devices to be shared and/or partitioned among a plurality of processing complexes within the load/store fabric of each of the processing complexes without requiring modification to the operating system or driver software of the processing complexes. The apparatus and method includes a switch for selectively coupling each of the processing complexes to one or more shared I/O devices. The apparatus and method further includes placing information within packets transmitted between the switch and the I/O devices to identify which of the processing complexes the packets are associated with. The invention further includes an apparatus and method within the shared I/O devices to allow the shared I/O devices to service each of the processing complexes independently.

Abstract: Computer-implemented method for enhancing cognition of a participant using visual emphasis. One or more scenes are provided and are available for visual presentation to the participant, each scene having a background and at least one foreground object. A scene is visually presented to the participant with a specified visual emphasis that enhances visual distinction of the at least one foreground object with respect to the background, where the foreground object(s) and/or the background are modified or selected to achieve the specified visual emphasis. The participant is required to respond to the scene, and a determination made as to whether the participant responded correctly. The visual emphasis may be modified based on whether or not the participant responded correctly a specified number of times. The presenting, requiring, and determining (and possibly the modifying) are repeated in an iterative manner to improve the participant's cognition.

Abstract: Provided are systems, methods and techniques for predicting a communication channel parameter. In one representative embodiment, values of a communication channel parameter are estimated at a plurality of previous points in time, values are predicted for the communication channel parameter at a plurality of such previous points in time, using a plurality of the channel estimates, and then the channel estimates are updated using the predictions, with the latter prediction and estimation steps being repeated until a specified condition has been satisfied.

Abstract: An apparatus and method is provided for allowing I/O devices to be shared and/or partitioned among a plurality of processing complexes within the load/store fabric of each of the processing complexes without requiring modification to the operating system or driver software of the processing complexes. The apparatus and method includes a switch for selectively coupling each of the processing complexes to one or more shared I/O devices. The apparatus and method further includes placing information within packets transmitted between the switch and the I/O devices to identify which of the processing complexes the packets are associated with. The invention further includes an apparatus and method within the shared I/O devices to allow the shared I/O devices to service each of the processing complexes independently.

Abstract: A method and system for providing acknowledgment and/or data rate control (DRC) information with respect to data packets conveyed on a plurality of active forward link (FL) carriers. The number of reverse link (RL) carriers employed for the acknowledgment and/or DRC information may be less than the number of active FL carriers, and may be a single carrier, even when the signaling protocol is, in the limit, consistent with presently-supported standardized CDMA protocols. Code multiplexing techniques are employed inventively to convey information for up to fifteen FL carriers on a single, standard CDMA channel designed to provide such signaling for only a single FL carrier at a time.

Abstract: A method, apparatus, and system permits an access terminal (“AT”) for a multi-carrier CDMA wireless communication system to concurrently receive data on N different-frequency carriers while restricting one or more parameters that affect data reception rate, so that limited resources of the AT will be sufficient to properly process data packets on the N carriers. The data rate controlling parameter may be “I,” the number of supported H-ARQ channels for one or more of the N carriers. A relationship may be defined between the number of supported forward and/or reverse link carriers, versus the number of supported H-ARQ channels and/or other data rate controlling parameters. Messages may enable identification of AT characteristics, and configuration and/or dynamic re-configuration of AT data communication capabilities that are related to different values of N and corresponding different data rate controlling parameters.