Abstract: System and method for developing cognitive skills in a student, utilizing a computing device to present stimuli and to record responses. A stimulus may be graphically presented to the student via the computing device, and the student may be required to respond to the stimulus. A determination may then be made as to the correctness of the student's response. The graphically presenting, requiring, and determining may be performed for each of a plurality of stimuli. Additionally, the graphically presenting, requiring, determining, and performing may be performed in an iterative manner to improve the cognitive skills of the student. Various exercises directed to different cognitive skills and learning approaches may utilize this basic framework, and may be performed in an iterative manner to build cognitive skills in the student.

Abstract: An apparatus and method is provided for allowing one or more processing complexes to share a disk controller, particularly a serial ATA (SATA) controller. Each processing complex utilizes its own load-store domain to couple to the shared SATA controller, either directly, or indirectly through a shared I/O switch. Ultimately, requests from the processing complexes are presented to the switch with operating system domain header (OSD header) information so that the shared SATA controller can determine which request came from which processing complex, and allocate resources accordingly. Upstream responses from the shared SATA controller include the OSD header so that the shared I/O switch can accurately route the responses to their respective processing complexes.

Abstract: A fast, accurate, low offset comparator may be configured with multiple gain stages. A low gain, low input impedance, and fully differential common-gate amplifier may be configured as a first stage in the multi-stage comparator, providing a wide bandwidth for small power consumption. The inputs of the comparator may comprise a pair of differential inputs at respective source terminals of gate-coupled metal oxide semiconductor (MOS) devices configured in the input stage of the common-gate amplifier. A pair of differential outputs of the first stage may be coupled to a pair of differential inputs of a second stage, which may be a differential input current-mirror amplifier that may perform differential to single-ended conversion.

Abstract: Provided are digital processing apparatuses and techniques for estimating the fractional exponentiation of the base number 2, i.e., 2f where f is a fractional value. In one representative embodiment, a calculation is made of a folded quantity, which is equal to 1?f if f is greater than a specified threshold and is equal to f otherwise; then, a function of the folded quantity is calculated; and finally, the function of the folded quantity is subtracted from the fraction f and 1 is added. In another embodiment, 2f is approximated by calculating 1+f? in the binary numbering system.

Abstract: A method and apparatus for decoding and de-interleaving a received encoded and interleaved signal, the method employing and the apparatus including a single decoder coupled to a common buffer, the common buffer size equal to a frame of the received signal and the method further employing, and the apparatus further including, an address controller that causes data to be de-interleaved when read from the buffer and data to be interleaved when written to the buffer.

Abstract: A novel method and apparatus for initiating a reverse link intergenerational handoff in a CDMA communication system is disclosed. The inventive reverse link intergenerational handoff initialization method and apparatus measures and compares parameters between a serving base station of one generation and a target base station of another generation to determine the best possible handoff initiation time instant for performing a reverse link intergenerational hard handoff. The method and apparatus can utilize one of several embodiments to determine the best possible handoff initiation time instant. A pilot signal strength embodiment determines a handoff initiation time instant based upon the total pilot signal strength of both a serving and target base station. The Eb/Nt embodiment determines a handoff initiation time instant based upon Eb/Nt (ratio of average power per bit to total received power spectral density) values of both a serving and a target base station.

Abstract: An apparatus and method is provided for allowing I/O devices to be shared and/or partitioned among a plurality of processing complexes within the load/store fabric of each of the processing complexes without requiring modification to the operating system or driver software of the processing complexes. The apparatus and method includes a switch for selectively coupling each of the processing complexes to one or more shared I/O devices. The apparatus and method further includes placing information within packets transmitted between the switch and the I/O devices to identify which of the processing complexes the packets are associated with. The invention further includes an apparatus and method within the shared I/O devices to allow the shared I/O devices to service each of the processing complexes independently.

Abstract: An apparatus and method is provided for allowing I/O devices to be shared and/or partitioned among a plurality of processing complexes within the load/store fabric of each of the processing complexes without requiring modification to the operating system or driver software of the processing complexes. The apparatus and method includes a switch for selectively coupling each of the processing complexes to one or more shared I/O devices. The apparatus and method further includes placing information within packets transmitted between the switch and the I/O devices to identify which of the processing complexes the packets are associated with. The invention further includes an apparatus and method within the shared I/O devices to allow the shared I/O devices to service each of the processing complexes independently.

Abstract: Provided is automatic gain control (AGC) in which a feedback filter has a parameter that is changed based on information regarding data-packet boundaries. In one representative embodiment, the bandwidth of the filter temporarily is increased, or the time constant of the AGC filter temporarily is decreased, within a vicinity of each actual or potential packet boundary.

Abstract: A system and method for filtering spurious transitions from a digital signal is disclosed. The system includes a latch, a timer, and a logic circuit. Upon a transition of the digital signal, the latch holds the digital signal to block any additional transitions and the timer, which is connected to the output of the latch, begins a timing operation that creates a filter pulse. The output of the timer is then combined with the digital signal to filter the spurious transitions that may occur after the transition of the signal. The timer is implemented as an integrator that generates a ramp signal using a stable current source and a comparator that trips when the ramp signal passes a threshold. Use of the integrator and comparator saves space and reduces the system's operating current compared to the conventional approach.

Abstract: Provided is a multi-layered transmission technique in which a signal indicating that a transmitted data packet has been correctly received by the receiver is provided from one communication layer to another. Based on that signal, the second layer releases the corresponding data from its retransmission buffer. As result, storage requirements for data waiting to be retransmitted, if necessary, often can be significantly reduced.

Abstract: An apparatus for preventing a collision between a vehicle and an end of a Metal Beam Guide Fence. A transition device is attached to a modified section of the Metal Beam Guide Fence. The transition device and modified section are configured to allow passage of cables of a High Tension Cable Barrier through the Metal Beam Guide Fence and the transition device. The High Tension Cable Barrier redirects the colliding vehicle away from the end of the Metal Beam Guide Fence. The transition device and modified section are also configured to interact with the cables of the High Tension Cable Barrier to transfer and spread the collision load from the high tension cables to the Metal Beam Guide Fence.

Abstract: Computer-implemented method for enhancing a participant's cognition, including, e.g., visual memory, utilizing a computing device to present visual stimuli for training, and to record responses from the participant. Multiple graphical elements are provided for visual presentation to the participant. A temporal sequence of a plurality of the graphical elements is visually presented, including displaying each graphical element in the sequence at a respective location in a visual field for a specified duration, then ceasing to display the graphical element. The presented graphical elements include at least two matching graphical elements. The participant is required to respond to the presented sequence, including indicating locations of matching graphical elements. A determination is made as to whether the participant responded correctly, and the duration modified based on the determining.

Abstract: A fast, accurate, low offset comparator may be configured with multiple gain stages. A low gain, low input impedance, and fully differential common-gate amplifier may be configured as a first stage in the multi-stage comparator, providing a wide bandwidth for small power consumption. The inputs of the comparator may comprise a pair of differential inputs at respective source terminals of gate-coupled metal oxide semiconductor (MOS) devices configured in the input stage of the common-gate amplifier. A pair of differential outputs of the first stage may be coupled to a pair of differential inputs of a second stage, which may be a differential input current-mirror amplifier that may perform differential to single-ended conversion.

Abstract: Spread spectrum clock generation (SSCG) using asymmetric triangular profiles to reduce electromagnetic interference (EMI). The asymmetric triangular profiles provide better peak power attenuation and a more uniform power spectrum spread than conventional symmetric triangular profiles. The method receives a first clock signal that has a first frequency spectrum and modulates it with an asymmetric triangular profile to produce a second clock signal. The second clock signal has a wider frequency spectrum than the first clock signal and results in reduced electromagnetic interference compared with the first clock signal.

Abstract: A small booklet binding machine is presented for use in financial institutions to produce onsite, in an economical and expedient fashion, bound booklets for use as checkbooks, loan coupon books, or other forms of small booklets. A user places paper stock to be processed by the machine into an input tray. The user then places backer cards into the machine. The machine automatically advances the paper stock through a pair of rollers, which substantially slit the paper stock into a plurality of checks which are collated in a collector tray. When the machine has advanced and slit all of the paper stock in the input tray, the collector tray rotates to allow a stapler to secure the plurality of checks to the backer cards. The collector tray then rotates to allow a user to remove the bound checks from the machine. Operationally, the machine produces bound checkbooks, or loan coupon books, without user intervention, other than supplying the machine with backer cards.

Abstract: An apparatus and method is provided for allowing I/O devices to be shared and/or partitioned among a plurality of processing complexes within the load/store fabric of each of the processing complexes without requiring modification to the operating system or driver software of the processing complexes. The apparatus and method includes a switch for selectively coupling each of the processing complexes to one or more shared I/O devices. The apparatus and method further includes placing information within packets transmitted between the switch and the I/O devices to identify which of the processing complexes the packets are associated with. The invention further includes an apparatus and method within the shared I/O devices to allow the shared I/O devices to service each of the processing complexes independently.

Abstract: A switching power regulator for performing DC-to-DC conversion may be implemented with a soft-start circuit configured to ensure orderly power-up of the switching power regulator by controlling the maximum output current delivered to a load while maintaining proper voltage regulation during start-up. The soft-start circuit may use combinations of reference voltages generated by a reference voltage digital-to-analog converter and a programmable width burst-pulse to control an output voltage of the switching power regulator during start-up without requiring external components. The soft-start circuit may provide burst-pulses directly to a drive circuit configured in the switching power regulator to control the output voltage of the switching power regulator, thereby beginning to ramp up the output voltage of the switching power regulator from zero volts.

Abstract: A power bus for use in an IC is disclosed that is configured as a grid and further formed using strips formed on I/O pads such as data I/O and multi-level voltage I/O pads. An IC is disclosed comprising a power supply I/O pad and a data I/O pad which are made of a deposited conductor. The power supply I/O pad is connected to a power bus and the data I/O pad is connected to circuitry. A strip of deposited conductor is formed closely adjacent to the data I/O pad wherein the strip is connected to the power bus. Parallel paths are developed within the integrated circuit to distribute power within the circuit. A similar approach is taken with respect to multi-level I/O pads. The power bus provide for reduced IR drops and better power supplies to core logic within an integrated circuit.

Abstract: A step-down switching voltage regulator may operate in PFM mode based on peak current sense without requiring an external diode. The regulator may comprise a PMOS transistor and an NMOS transistor whose drains are coupled to a common output node and whose sources are coupled to high and low supply voltages, respectively, configured to develop a current in an inductor and generate an output voltage. A control circuit, coupled to the respective gates of the PMOS transistor and the NMOS transistor, may sense the current in the inductor (IL), sense an attenuated version of the output voltage (VFB), and sense the polarity of the voltage (VX) developed at the common output node. The control circuit may turn on the PMOS transistor when the VFB falls below a reference voltage and VX remains positive with respect to the low supply voltage, and may turn off the PMOS transistor when IL reaches a specified value or when VFB exceeds the reference voltage.