Abstract: A branch target address prediction mechanism is provided. A branch target buffer (BTB) is employed to predict target address only of indirect branch instructions. Return addresses are predicted from a call/return stack and PC-relative branch instructions are predicted by directly calculating the target address using a program counter-relative displacement specified in the instruction. Because the BTB only stores indirect branch instruction target addresses, the likelihood of aliasing collisions in the BTB is greatly reduced, thereby increasing the prediction accuracy of the BTB.

Abstract: An apparatus and method are provided for speculatively pairing micro instructions for parallel execution within a single pipeline of a microprocessor and subsequently splitting the paired micro instructions in the same clock cycle as the pairing if a resource conflict or operand dependency is detected. The apparatus includes multiplexing logic that feeds back a second of a pair of micro instructions stored in an instruction register back into the instruction register for sequential execution after the first micro instruction if a translator detects late in the clock cycle that a resource conflict or operand dependency exists. An instruction pair indicator is provided along with the pair of micro instructions down to the execution stages to inform the execution stages whether the second micro instruction is valid for parallel execution with the first micro instruction. The method may also be used in conjunction with a micro instruction queue.

Abstract: An on-chip split transaction system bus having separate address and data portions is provided. The system bus contains separate address and data buses for initiating and tracking transactions on either or both of the address or data portions of the bus. The system bus provides communication via a bus interface that includes split transaction tracking and control to establish transaction ID's for each transaction initiated by the bus interface, and to determine whether data appearing on the data portion of the system bus is associated with one of its pending transactions. The bus interface also contains a data release mechanism to reduce turn around time of the data bus between competing data bus masters. The data release mechanism is incorporated within the bus interface of all data bus masters. A data bus master drives data release during the last cycle of a data transaction.

Abstract: A method for training of auditory and graphical discrimination in humans, and a human's short term memory, is provided within an animated game environment. The method provides a number of stimulus sets, each stimulus set having similar sounding phonemes associated with graphemes. Upon initiation of a trial, a grid of tiles is presented to a subject. The subject selects the tiles, one at a time. As the tiles are selected, an associated phoneme is presented to the subject. The subject clears away tiles by pairing them with identical tiles. When all the tiles in a trial are cleared, the subject is either promoted or demoted in skill level. Promotion/demotion varies the number of tiles presented, the phonemes used within each trial, and the amount of audio processing that is applied to the phonemes.

Abstract: An Infiniband channel adapter for performing direct data transfers between a PCI bus and an Infiniband link without double-buffering the data in system memory. A local processor programs the channel adapter to decode addresses in a range of the PCI bus address space dedicated to direct transfers. When an I/O controller attached to the PCI bus transfers data from an I/O device to an address in the dedicated range, the channel adapter receives the data into an internal buffer and creates an Infiniband RDMA Write packet for transmission to virtual address within a remote Infiniband node. When the channel adapter receives an Infiniband RDMA Read Response packet, the channel adapter provides the packet payload data to the I/O controller at a PCI address in the dedicated range. A plurality of programmable address range registers facilitates multiple of the direct transfers concurrently by dividing the dedicated address range into multiple sub-ranges.

Abstract: An apparatus and method are provided for determining initial information about a macro instruction prior to decoding of the macro instruction by translation logic within a pipeline microprocessor. The apparatus includes an instruction cache divided into a number of cache ways, each of the cache ways storing a number of cache lines that have been retrieved from memory. As a linear address within a next instruction pointer is provided to retrieve a the macro instruction from the cache, indexed cache lines from each of the cache ways are predecoded by predecode logic. Predecoding is performed in parallel with translation of the linear address to a physical address by translation lookaside buffer logic. The bytes of the indexed cache lines, along with corresponding predecode information fields, are provided to way selection logic.

Abstract: A tag-based write-combining apparatus in a microprocessor. The apparatus includes a register that stores the store address of the last write-combinable store passing through the store stage of the pipeline. Tag allocation logic compares the last store address with the store address of a new store and allocates the same tag as was previously allocated to the last store if the addresses are in the same cache line, and assigns the next incremental tag otherwise. Tag registers store write buffer tags associated with store data in write buffers waiting to be written to memory on the processor bus. When the new store reaches the write buffer stage, tag comparators compare the new store tag with the write buffer store tags. If the tags match, the write buffer control logic combines the new store data with the store data in the write buffer with the matching tag.

Abstract: An apparatus and method are provided for synthesizing a variable frequency sinusoidal waveform. The apparatus and method exploit octant symmetry properties of sine and cosine waveforms, when taken together. The digital frequency synthesis apparatus includes a phase signal and a phase-to-amplitude converter. The phase signal indicates a desired phase angle of the sinusoidal waveform. The phase-to-amplitude converter is coupled to the phase signal. The phase-to-amplitude converter provides a desired amplitude sample corresponding to the desired phase angle, where the desired amplitude sample is derived from amplitude samples corresponding to an octant of the sinusoidal waveform. The phase-to-amplitude converter includes a Haar Transform-based coarse octant amplitude sample generator that computes Haar coefficients corresponding to the phase signal and transforms the Haar coefficients into the desired amplitude sample.

Abstract: An apparatus and method are provided for improving the speed at which a pipeline microprocessor accesses misaligned memory operands. The apparatus includes page boundary evaluation logic and address logic. The page boundary evaluation logic evaluates an address corresponding to the misaligned memory operand, and determines whether or not access to the misaligned memory operand is within a single memory page. The address logic is coupled to the page boundary evaluation logic. When access to the misaligned memory operand is within the single memory page, the address logic eliminates an access tickle instruction from an instruction sequence generated to access the misaligned memory operand.

Abstract: An apparatus and method are provided for accurately predicting the outcome of branch instructions prior to their execution by a pipeline microprocessor. The apparatus has a static branch predictor, a mandatory signal, and a biased prediction correlator. The static branch predictor provides a predicted outcome for a branch instruction, and determines if the branch instruction is a biased outcome conditional branch instruction. The mandatory signal is coupled to the static branch predictor and indicates whether or not the branch instruction is the biased outcome conditional branch instruction, thereby indicating whether or not the predicted outcome takes precedence over a dynamic branch prediction for the branch instruction. The biased prediction correlator is coupled to the static branch predictor and the mandatory signal. The biased prediction correlator receives the predicted outcome, the mandatory signal, and the dynamic branch prediction.

Abstract: An apparatus and method are provided for performing both forward and inverse Haar transforms of a sequence of n-bit data samples. The forward Haar transform apparatus has sum-and-truncate logic and a plurality of coefficient generators. The sum-and-truncate logic generates a plurality of n-bit intermediate terms. The plurality of coefficient generators is coupled to the sum-and-truncate logic. The plurality of coefficient generators generate a plurality of n+1-bit spectral coefficients. The inverse Haar transform apparatus has index signal and inverse transform logic. The index signal indicates a specific n-bit sample, the specific n-bit sample being one of a sequence of n-bit samples corresponding to the Haar transform. The inverse transform logic is coupled to the index signal. The inverse transform logic computes the specific n-bit sample, where the specific n-bit sample is derived from selected n+1-bit spectral coefficients.

Abstract: An apparatus and method within a pipeline microprocessor are provided for allocating a cache line within an internal data cache upon a write miss to the data cache. The that apparatus and method allow data to be written to the allocated cache line before fill data for the allocated cache line is received from external memory over a system bus. The apparatus includes write allocate logic and a write buffer. The write allocate logic allocates the cache line within the data cache, it stores data corresponding to the write miss within the allocated cache line, and queues a speculative write command directing an external bus to store said the data to the external memory in the event that transfer of the fill data is interrupted. The speculative write command is stored in the write buffer and, in the event of an interruption such as a bus snoop to the allocated cache line, the write buffer issues the speculative write command to the system bus, thereby writing the data to external memory.

Abstract: A data cache in an in-order single-issue microprocessor that detects cache misses generated by instructions behind a stalled instruction in the microprocessor pipeline and issues memory requests on the processor bus for the missing data so as to overlap with resolution of the stalled instruction, which may also be a cache miss, is provided. The data cache has pipeline stages that parallel portions of the main pipeline in the microprocessor. The data cache employs replay buffers to save the state, i.e., instructions and associated data addresses, of the parallel data cache stages so that instructions above the stalled instruction can continue to proceed down through the data cache and access the cache memory to generate cache misses. The data cache restores the data cache pipeline stages upon detection that stall will terminate. The data cache also detects TLB misses generated by instructions subsequent to the stalled instruction and overlaps page table walks with the stall resolution.

Abstract: A branch predictor for improving branch prediction accuracy is provided. The branch predictor includes global and local Agree dynamic branch predictors, one of which is selected for correlation with a static branch prediction made based upon a test type of a conditional branch instruction specifying a condition upon which the branch will be taken. In one embodiment, the selection is made by correlating a selection prediction made the static predictor based on the test type and an Agree prediction made by a selector history table based on the branch instruction address. In an alternate embodiment, the selection is made directly by the selector history table, without the benefit of the static prediction. In addition, the static predictor makes its predictions based upon an opcode of an instruction preceding the conditional branch instruction and upon a sign of a displacement for calculating a target address of the conditional branch instruction.

Abstract: An apparatus and method are provided for accurately predicting the outcome of branch instructions prior to their execution by a pipeline microprocessor. The apparatus includes a bias indicator and a dynamic branch predictor. The bias indicator receives a branch instruction from an instruction buffer and provides an output indicating a particular outcome bias category for the branch instruction. The bias indicator provides the output as a function of a branch type and a displacement, where the branch type and the displacement are prescribed by the branch instruction The dynamic branch predictor is coupled to the bias indicator.

Abstract: An apparatus and method for improving microprocessor performance by improving the prediction accuracy of conditional branch instructions is provided. A dynamic branch predictor speculatively updates global branch history information based on the prediction of a first branch instruction so that the predictor can predict the outcome of a second branch instruction following closely in the pipeline with the benefit of the first prediction. This improves the prediction accuracy where the first branch has not been resolved prior to the time when the second prediction is ready to be made. If the first prediction turns out to be incorrect, the global branch history is restored from a previously saved copy and updated with the first branch instruction's actual outcome.

Abstract: An apparatus and method are provided that enable system designers to have programmable minimum memory page sizes. The apparatus has a memory management unit (MMU) for storing a plurality of page table entries (PTEs) and a pagegrain register for prescribing a minimum page size. Each of the PTEs in the MMU specifies a page granularity for a corresponding physical memory page, where the page granularity is bounded by the minimum page size. The MMU has and page granularity logic. The page granularity logic determines a page size for the corresponding physical memory page. The page size is determined based on the minimum page size and the page granularity. The pagegrain register prescribes the minimum page size, in default, according to a legacy memory management protocol, and in alternative, as one of the programmable minimum memory page sizes according to an extended memory management protocol.

Abstract: An apparatus and method are provided for performing a floating point exchange operation in a pipeline microprocessor in zero effective clock cycles. The present invention exploits the pattern of floating point operations common to most floating point software algorithms where floating point exchange operations appear as every other instruction between floating point computational instructions. The apparatus includes translation logic, that pairs the operations directed by a floating point macro instruction and a floating point exchange macro instruction by generating a micro instruction with an exchange extension. The exchange extension directs the microprocessor to perform the floating point exchange operation in parallel with the operation prescribed by the floating point macro instruction within a single floating point unit.

Abstract: A hardware-based random number generator is provided for incorporation within an integrated circuit. The apparatus has a first variable frequency oscillator, a second variable frequency oscillator, and a variable bias generator. The first variable frequency oscillator generates a first oscillatory signal at a first frequency. The a second variable frequency oscillator generates a second oscillatory signal that is asynchronous to the first oscillatory signal and has a second frequency less than the first frequency, where bits of the random number are configured from samples of the first oscillatory signal taken at the second frequency. The variable bias generator is coupled to the first and second variable frequency oscillators, and generates an analog bias signal. The first and second frequencies vary according to the analog bias signal, and the analog bias signal varies based upon logic states of a plurality of bits of the random number.

Abstract: An apparatus and method within a pipeline microprocessor are provided for allocating a cache line within an internal data cache upon a write miss to the data cache. The apparatus and method allow data to be written to the allocated cache line before fill data for the allocated cache line is received from external memory over a system bus. The apparatus includes write allocate logic and a fill controller. The write allocate logic stores first bytes within the cache line corresponding to the write, and updates remaining bytes of the cache line from memory. The fill controller is coupled to the write allocate logic. The fill controller issues a fill command over the system bus directing the external memory to provide the remaining bytes, where the fill command is issued in parallel with storage of the first bytes within the cache line.