Abstract: A method for monitoring the performance of a catalytic converter (34) computes the oxygen storage capacity and desorption capacity of a catalyst within the catalytic converter (34). An engine control unit (10) receives mass flow rate information of air from a mass air flow rate sensor (12) and an injector driver (24), and receives electrical signals from an upstream exhaust gas sensor (28) and a downstream exhaust gas sensor (30). The engine control unit (10) calculates normalized air fuel ratios for the exhaust gas entering and leaving the catalytic converter (34) and performs numerical integration to determine the oxygen storage capacity and oxygen desorption capacity of the catalyst in the catalytic converter (34). The calculated oxygen storage and desorption capacities of the catalyst are compared with threshold values to determine the performance of the catalytic converter (34).

Abstract: A method for monitoring and controlling the performance of a catalytic converter (34) includes monitoring an exhaust gas stream from an engine (16) for the presence of methane. Upon detecting methane in the exhaust gas stream an oxygen storage level of a catalyst within the catalytic converter (34) is determined. The oxygen storage level is compared with a reference standard and the air/fuel ratio of the exhaust gas stream is continuously adjusted to maintain the oxygen storage level within predetermined control limits.

Abstract: A sealing composition (134) includes about 85-95 wt. % glass frit, about 2-8 wt. % butyl carbitol acetate, about 2-8 wt. % alpha-terpineol, about 0.05-0.8 wt. % ester alcohol, and about 0.05-0.8 wt. % low molecular weight ethyl cellulose binder. A method for fabricating an apparatus (100) includes the steps of applying the sealing composition (134) to a portion (132) of the apparatus (100), removing the butyl carbitol acetate, the alpha-terpineol, and the ester alcohol, removing the binder, and heating the glass frit to a sealing temperature of the glass frit.

Abstract: A field emission device (100, 200) includes an anode (190); a substrate (110); a plurality of spaced apart cathodes (120); a dielectric layer (124) disposed on the cathodes (120); a plurality of spacer pads (130, 230) disposed on the substrate (110) between adjacent cathodes (120) and including a spacer contact layer (142, 185) that defines the surfaces of the spacer pads (130, 230); a spacer (150) having a first edge (157), a second edge (155), and a conductive layer (152) disposed on the second edge (155), the first edge (157) contacting the anode (190), the conductive layer (152) contacting the spacer contact layer (142, 185) at the spacer pads (130, 230); and an electron emitter (170) disposed within the dielectric layer (124) and spaced apart from the second edge (155) of the spacer (150).

Abstract: An edge emission FED (100) includes a supporting substrate (110); a cathode (120) disposed on the supporting substrate (110); a ballast layer (130) disposed on the cathode (120); an emissive layer (140) disposed on the ballast layer (130) and defining an emissive edge (183); a field shaper layer (150) disposed on the emissive layer (140); a dielectric layer (160) disposed on the field shaper layer (150); a gate extraction electrode (170) disposed on the dielectric layer (160); an emission well (180) defined by the ballast layer (130), the emissive edge (183), the field shaper layer (150), the dielectric layer (160), and the gate extraction electrode (170); and an anode plate (188) opposing the gate extraction electrode (170).

Abstract: A solenoid driver (10) capable of detecting the operational status of a solenoid (12) including the position of an armature within a solenoid coil and an operational method. The solenoid driver (10) generates a first solenoid current within the solenoid (12) and measures a first decay time t.sub.1. The first solenoid current is insufficient to pull the armature into the coil of the solenoid (12). A comparator circuit (22) continuously monitors the solenoid current and initiates a timer within a counter circuit (34) to compute the first current decay time. A second solenoid current is generated within the solenoid (12) that is sufficient to pull the armature into the coil of the solenoid (12). The second solenoid current is turned off and a second decay time t.sub.2 is measured. The decay times are stored in storage registers (R1, R2) within a controller (36). The controller (36) compares the measured decay times with stored values and outputs the armature position information over a communications bus (34).

Abstract: A field emission device (100) includes a supporting substrate (110) having a major surface; a cathode (111) disposed on the major surface of the supporting substrate (110); a dielectric layer (112) disposed on the cathode (111); a gate extraction electrode (114) disposed on the dielectric layer (112); the cathode (111), the dielectric layer (112), and the gate extraction electrode (114) defining a spacer well (132); an anode plate (104) opposing the gate extraction electrode (114); a spacer (106) extending between the cathode (111) at the spacer well (132) and the anode plate (104); a first spacer shield (108) disposed within the spacer well (132) and surrounding the spacer (106); and a second spacer shield (108) affixed to the anode plate (104) and surrounding the spacer (106).

Abstract: A pressure sensor (10) includes a base (12) supporting a lead frame (28) having a pressure sensing element (14) electrically coupled to the lead frame (28). The molded base (12) interlocks with first and second diaphragm mounting frames (18, 20) and together with first and second diaphragms (22, 24) forms first and second chambers (36, 40). An incompressible fluid resides in the first and second chambers (36, 40) and transfers the pressure of a sensed media impinging on either of the first or second diaphragms (22, 24) to the pressure sensing element (14). The incompressible fluid filling the first and second chambers (36, 40), together with the flexible and impermeable membrane material of the first and second diaphragms (22, 24) effectively isolates the pressure sensing element (14) from the sensed media.

Abstract: A method for monitoring the performance of a catalytic converter includes the monitoring of output from a first gas sensor (16) positioned upstream from a catalytic converter (12) and a second gas sensor (18) located at a position downstream from the catalytic converter (12). An engine controller (20) receives the output of the first and second gas sensors (16,18) and also receives estimates of the exhaust gas mass flow rate and the catalyst temperature within the catalytic converter (12). The exhaust gas mass flow rate and the catalyst temperature are used to calculate a mass transfer coefficient that is determinative of the conversion efficiency of the catalytic converter (12). A monitoring parameter is determined using the output of the first and second gas sensors (16,18), and the monitoring parameter is normalized to the coefficient.

Abstract: An electronic control module (10) includes a circuit substrate (12) containing a plurality of thermal vias (36) and a heat-generating electronic device (26) attached to the thermal vias (36). The circuit substrate (12) is attached to a mounting plate (18) by a plurality of electrically-isolated, thermal attachment pads (20) located at selected positions on an electrically insulating layer (16) overlying a metal baseplate (14). A solder layer (22) functions to both mechanically attach the plurality of thermal vias (36) to the plurality of thermal attachment pads (20), and to provide a thermal dissipation pathway for heat generated by the electronic devices (26). The heat is transferred from the circuit substrate (12) through the plurality of thermal attachment pads (20) to the metal baseplate (14).

Abstract: A selective gas sensor (10) for detecting a particular compound, or group of compounds, such as non-methane hydrocarbons, within a high temperature gas stream (12) includes an oxygen generation system (14) positioned over an oxygen diffusion region (15). The oxygen generation system (14) and the oxygen diffusion region (15) provide oxygen through a medial temperature control zone (20) to a sensing element (16). The temperature and flux of hydrocarbon components within the high temperature gas stream (12) are regulated by components within the high temperature control zone (20) and by an external temperature control zone (22) in thermal contact with the sensing element (16).

Abstract: An electronic control module (10) includes a package substrate (12) having an interior cavity (28) through which a package lead (22) traverses. The interior cavity (28) is filled with an expandable polymer material (34). The expandable polymer material (34) is constrained within the cavity by a pressure resistive layer (32, 35) that overlies expandable polymer material (34) In one embodiment, an epoxy layer (32) forms an upper surface of the interior cavity (28). The expandable polymer material (34) is responsive to a fluid, such that upon contact with a fluid diffusing along the package lead (22), the expandable polymer material (34) will swell and form a fluid-tight pressure seal around the package lead (22). The fluid-tight pressure seal prevents the fluid from diffusing to interior portions of the electronic control module (10) and causing the failure of electronic components (18) mounted within the electronic module (10).

Abstract: A process for fabricating a metallized interconnect structure in a semiconductor device includes the steps of depositing a first aluminum layer (22) into a via opening (16) in a dielectric layer (18). A doping layer (24) is deposited by high density plasma sputtering to form a portion thereof in the bottom of the via opening (16). A second aluminum layer (26) is chemical vapor deposited to overlie the doping layer (24) and to fill the via opening (16). An annealing process can then be carried out to diffuse metal dopants from the doping layer (24) into nearby metal regions to provide a uniformly doped metal region within the via opening (16).

Abstract: A semiconductor device includes a pass transistor (28) electrically coupled to a driver transistor (16) by a common drain region (52). The pass transistor (28) includes the pass gate electrode (44) having a polycrystalline silicon layer (68). The driver transistor (16) includes a driver gate electrode (40) having a polycrystalline silicon layer (74). The dopant concentration in polycrystalline silicon layer (74) is greater than the dopant concentration in polycrystalline silicon layer (68). The differential and dopant concentration between the pass gate electrode (44) and the driver gate electrode (40) results in a greater current gain in the driver transistor (16) relative to the pass transistor (28). When incorporated into an SRAM memory cell (10), the driver transistor (16) and the pass transistor (28) provide greater cell stability by improving the immunity of the cell to electrical disturbance through the pass transistor (28).

Abstract: A process for fabricating a graded-channel MOS device includes the formation of a masking layer (16) on the surface of a semiconductor substrate (10) and separated from the surface by a gate oxide layer (12). A first doped region (22) is formed in a channel region (20) of the semiconductor substrate (10) using the masking layer (16) as a doping mask. A second doped region (24) is formed in the channel region (20) and extends from the principal surface (14) of the semiconductor substrate (10) to the first doped region (22). A gate electrode (34) is formed within an opening (18) in the masking layer (16) and aligned to the channel region (20). Upon removal of the masking layer (16) source and drain regions (36, 38) are formed in the semiconductor substrate (10) and aligned to the gate electrode (34).

Abstract: A process for the fabrication of a non-silicided region in an integrated circuit includes the fabrication of a silicide blocking layer (24, 46, 54, 92, 112). In one embodiment, a field transistor (80) is formed by depositing a silicide blocking layer (84) overlying a field gate electrode (70) and source and drain regions (76, 78). A carbonaceous mask (86) is formed on the silicide blocking layer (84) overlying the field transistor (80). A partial etching process is performed to remove a portion of the silicide blocking layer (84) exposed by the carbonaceous mask (86). Then, the carbonaceous mask (86) is removed and the etching process is continued to completely remove portions of the silicide blocking layer (84) not originally protected by the carbonaceous mask (86). The etching process forms a silicide blocking layer (92) overlying the field transistor (80) and sidewall (94) adjacent to an MOS gate electrode (68).

Abstract: A process for fabricating a semiconductor device which includes forming a collimated metal layer (54) on the surface of a semiconductor substrate (24), while maintaining the temperature of the substrate preferably below about 100.degree. C., and most preferably below about 25.degree. C. The collimated metal layer (54) is formed by directing a stream of metal atoms through a collimator (18) and onto the surface of the substrate (24). The temperature of the substrate (24) is controlled by supplying a heat transfer fluid from a temperature control system (26) to a vacuum chuck (14) supporting the semiconductor substrate (24). The collimated metal layer (54) is comprised of metal atoms having predominantly a (002) crystallographic orientation. The uniform crystallographic orientation of the collimated metal layer (54) can be used to effect the formation of additional metal layers (58, 62) having uniform crystallographic orientation.

Abstract: A thin-film transistor and SRAM memory cell include thin-film source and drain regions (12, 14) separated by an opening (22) and overlying and insulating layer (11). A thin-film channel layer (16) overlies the thin-film source and drain regions (12, 14) and a portion of the insulating layer (11) exposed by the opening (22). A thin-film gate electrode (20) is positioned in the opening (22) and defines a thin-film channel region (24) in the thin-film channel layer (16). The thin-film gate electrode (20) is separated from the thin-film channel region (24) by a gate dielectric layer (18). The thin-film channel region (24) extends along vertical wall surfaces (26, 28) of the thin-film source and drain regions (12, 14) providing an extended channel length for the thin-film transistor.

Abstract: A process for the fabrication of an MOSFET device includes the formation of a buffer layer (28) overlying the surface of a semiconductor substrate (14) adjacent to a gate electrode (18). A defect compensating species is diffused through the buffer layer (28) and through a gate dielectric layer (12) to form a defect-compensating region (30) at the surface (14) of the semiconductor substrate (10). The defect-compensating region (30) in conjunction with the buffer layer (28) minimize and control the population of point defects in the channel region (22) of the semiconductor substrate (10). By controlling the population of point defects in the channel region (22), a substantially uniform doping profile is maintained in a shallow doped region (16) formed in the semiconductor substrate (10) at the substrate surface (14). The maintenance of a uniform doping profile in the shallow doped region (16) results in improved threshold voltage stability as the lateral dimension of the channel region (22) is reduced.

Abstract: A process for fabricating refractory-metal silicide layers in a semiconductor device includes the formation of a composite gate electrode (54) and a buried contact structure (56). The composite gate electrode (54) includes a refractory-metal silicide layer (52) separated from a first polycrystalline silicon layer (38) by a diffusion barrier layer (46). The buried contact structure (56) includes a refractory-metal silicide layer (52) separated from a buried contact region (44) of a semiconductor substrate (30) by the diffusion barrier layer (46). The refractor-metal silicide layer (52) is formed by inverting a second polycrystalline silicon layer (48) to a refractory-metal silicide material while preventing the diffusion of refractory-metal atoms into underlying silicon regions.