Abstract: A monolithic semiconductor body (26) resides in an opening (16) formed in an insulating layer (14). The monolithic semiconductor body (26) includes an elongated region (20) filling the opening (16) in the insulating layer (14) and contacting a semiconductor region (12). The monolithic semiconductor body (26) further includes a surface region (24) overlying the elongated region (20) and a portion of the surface (22) of the insulating layer (14) adjacent to the opening (16). The monolithic semiconductor body (26) is fabricated by first depositing a layer of semiconductor material into the opening (16), then planarizing the surface of the insulating layer (14). Next, a selective deposition process is carried out to form the surface region (24) using the semiconductor material in the opening (16) as a nucleation site. The radius of curvature of the surface region (24) is determined by the amount of controlled overgrowth during the selective deposition process.

Abstract: A semiconductor device (10) includes first and second electrically coupled MOS transistors (16, 28) in which the current gain of the second MOS transistor (16) is greater than the current gain of the first MOS transistor (28). Higher carrier mobility is obtained in the second MOS transistor (16) relative to the first MOS transistor (28) by fabrication of the second MOS transistor (16) as a buried channel device. The first MOS transistor (28) includes a gate electrode (44) of the second conductivity type separated from a channel region (46) of the first conductivity type by a gate electric layer (48). The second MOS transistor (16) includes a gate electrode (40) of a first conductivity type overlying a substrate (11) also of the first conductivity type. A channel surface layer (60) of a second conductivity type resides in the substrate (11 ) and is separated from the gate electrode (40) by a gate dielectric layer (58).

Abstract: A chemical-mechanical-polishing process in which energy is imparted to a polishing pad (18) dislodging particles (46), which are removed by vacuum withdrawal to continuously clean the surface of the polishing pad (14). Energy is imparted to polishing pad (18) by either sonic energy from acoustic waves, or by physical impaction. The acoustic waves are generated by submerging a transducer (28) in the polishing slurry (18). The transducer (28) is powered by a voltage amplifier (30) coupled to a computer controlled-frequency generator (32). The acoustic wave frequency is adjusted by the frequency generator (32) to induce sonic vibration in the polishing pad (14) such that particles (46) are continuously dislodged from polishing pad (14). Physical impaction is performed by an impaction tool (48) coupled to a vacuum head (33).

Abstract: A metal interconnect structure includes copper interface layers (24, 30) located between a refractory metal via plug (28), and first and second metal interconnect layers (16, 32). The copper interface layers (24, 30) are confined to the area of a via opening (22) in an insulating layer (20) overlying the first interconnect layer (16) and containing the via plug (28). The interface layers (24, 30) are subjected to an anneal to provide copper reservoirs (36, 37) in the interconnect layers (16, 32) adjacent to the interface layers (24, 30). The copper reservoirs (36, 37) continuously replenish copper depleted from the interface when an electric current is passed through the interconnect structure. A process includes the selective deposition of copper onto an exposed region (23) of the first metal interconnect layer (16), and onto the upper portion the via plug (28), followed by an anneal in forming gas to form the copper reservoirs (36, 37).

Abstract: A distillable, non-azeotropic solvent mixture for electronic assembly cleaning in order to adequately remove solder flux and other residues traditionally removed using CFC-based azeotropes. The mixture is heated to at least the boiling point of component A but less than the boiling point of component B. Component A vaporizes (102), forming a vapor layer above the mixture (103). Condensing elements (101) near the top of the cleaning apparatus condense the vapor (102), returning it to the heated mixture (103) to be vaporized again. The assembly (104) to be cleaned is lowered through the vapor and then immersed in the mixture (103) before being positioned in the vapor (102).

Abstract: A selective cleaning process for fabricating a semiconductor device includes the steps of processing a semiconductor substrate (10) and introducing metal contaminants (22) by contacting the semiconductor substrate (10) with a polishing slurry during a polished planarization process. The metal contaminants (22) are removed by applying a cleaning solution including an organic solvent and a compound containing fluorine. The chemical constituents of the cleaning solution are substantially unreactive with metal interconnect material (12) underlying dielectric layers (18) present on the semiconductor substrate (10). The preferred cleaning solution comprises an aqueous solution of ethylene glycol and ammonium fluoride.

Abstract: A process for fabricating an improved nonvolatile memory device includes the formation of a control gate electrode (70) which overlies a floating gate electrode (42) and is separated therefrom by an inter-level-dielectric layer (62). The control gate electrode (70) and the underlying floating gate electrode (42) form a stacked gate structure (72) located in the active region (44) of a semiconductor substrate (40). An electrically insulating sidewall spacer (54) is formed at the edges of the floating gate electrode (42) and electrically isolates the control gate (70) from the semiconductor substrate (40). During the fabrication process, implanted memory regions (56, 58) are formed in the active region (44) prior to the formation of control gate electrode (70). A word-line (68) and the control gate (70) are formed by anisotropic etching of a semiconductor layer (66), which is deposited to overlie inter-level-dielectric layer (62).

Abstract: A cross-point EEPROM memory array includes a semiconductor substrate (10) having first and second bit-lines (32, 34) spaced apart by a channel region (36). A control gate electrode (24) is formed by a portion of a control gate line, which overlies a first portion of the channel region (36) and is separated therefrom by an ONO layer (17). A select gate electrode (40) is formed by a portion of a select gate line disposed on the substrate (10) perpendicular to the control gate line. Individual cells in the array are programmed by injecting electrons using source-side injection into trapping sites (19) in the silicon nitride layer (14) of the ONO layer (17). The cells in the array are erased by electron tunneling through the top silicon dioxide layer (16) of the ONO layer (17), and are dissipated in the control gate electrode (24).

Abstract: A process for the fabrication of an X-ray absorbing mask includes providing a silicon substrate (10) having a front surface (16) and a back surface (18). A membrane layer (12) is formed on the front surface (16). In one embodiment of the invention, an etch stop layer (14) and an X-ray absorbing layer (20) are sequentially formed over the membrane layer (12). In a preferred embodiment, the X-ray absorbing layer (20) is tantalum silicon nitride deposited by RF sputter deposition directly onto the layers overlying the silicon substrate (10). The structure is then annealed at a temperature sufficient to reduce the internal stress in the X-ray absorbing layer (20). Finally, the X-ray absorbing layer is patterned to form a masking pattern (30, 36) on the membrane layer (12).

Abstract: A semiconductor memory cell (10) includes first and second cross-coupled driver transistors (13, 19) each having a source-drain region and a channel region formed in a first thin-film layer (36, 36'). First and second parallel opposed wordlines (20, 22) overlie a single-crystal semiconductor substrate (12) and the channel region (46) of each driver transistor overlies a portion of an adjacent wordline. A portion of the thin-film layer (36, 36') makes contact to the single-crystal semiconductor substrate (12) adjacent to the opposite wordline. The channel and source-drain regions of first and second load transistors (15, 21) are formed in a second thin-film layer (64) which overlies the driver transistors (13, 19). The load transistors (15, 21) are cross-coupled to the driver transistors (13, 19) through common nodes (31, 33).

Abstract: An improved planarization process includes the steps of forming recessed regions (38) and elevated regions (34) in a semiconductor substrate (30). The substrate is oxidized to form an oxide liner (39) overlying the recessed regions, and a fill material (40) is deposited to overlie the substrate (30) filling the recessed regions (38). An etching process is used to remove portions of the fill material (40) and to expose portions of a first planarization layer (44) overlying the elevated regions (34) of the substrate (30). The fill material is etched and a second planarization layer (46) is deposited to overlie dielectric portions (42), and portions (44) of first planarization layer (32) exposed by the etching process. A chemical-mechanical-polishing process is then carried out to form a planar surface (47), and remaining portions of the planarization layers and fill material are removed.

Abstract: A method for the fabrication of a trench isolation region (44) includes the deposition of first, second, and third oxidizable layers (28, 34, 42). The first oxidizable layer (28) is deposited to overlie the surface of a trench (12) formed in a semiconductor substrate (10). The first oxidizable layer (28) also fills a recess (26) formed in a masking layer (14), and resides adjacent to the upper surface of the trench (12). After oxidizing the first oxidizable layer (28), a second oxidizable layer (34) is deposited to fill the trench (12). A third oxidizable layer (42) is deposited to overlie the second oxidizable layer (34) and fills a remaining portion of the recess (26). An oxidation process is performed to oxidize oxidizable layer (42) and a portion of second oxidizable layer (34) to form a trench isolation region (44). In an alternative embodiment of the invention, a shallow isolation region (46) is formed in proximity to the trench isolation region ( 44).

Abstract: A metal interconnect structure includes copper interface layers (24, 30) located between a refractory metal via plug (28), and first and second metal interconnect layers (16, 32). The copper interface layers (24, 30) are confined to the area of a via opening (22) in an insulating layer (20) overlying the first interconnect layer (16) and containing the via plug (28). The interface layers (24, 30) are subjected to an anneal to provide copper reservoirs (36, 37) in the interconnect layers (16, 32) adjacent to the interface layers (24, 30). The copper reservoirs (36, 37) continuously replenish copper depleted from the interface when an electric current is passed through the interconnect structure. A process includes the selective deposition of copper onto an exposed region (23) of the first metal interconnect layer (16), and onto the upper portion the via plug (28), followed by an anneal in forming gas to form the copper reservoirs (36, 37).

Abstract: A process for fabricating a metallization structure includes the formation of an interlayer (20) using an MOCVD deposition process. A metal-organic precursor, having as one component tungsten, is used to deposit the interlayer (20) onto a surface region (18) of a substrate (10) at the bottom of an opening (16). The MOCVD deposition process forms a conformal layer which evenly coats all surfaces of the opening (16). Next, a refractory metal layer (22) is deposited to overlie the interlayer (20). Because of conformal nature of the MOCVD deposition process, refractory metal layer can be formed using corrosive gasses such as tungsten hexafluoride.

Abstract: A voltage controlled resistive device is provided by coupling a vertical bipolar transistor (34) with a junction field effect transistor (36) through a well region 18, which functions as both a drain region for the junction field effect transistor (36), and as a collector region for the vertical bipolar transistor (34). The voltage controlled resistive device of the invention provides a means of varying the output current of the vertical bipolar transistor (34) by application of a variable voltage level to the gate region (26) of the junction field effect transistor (36). To obtain proper junction bias characteristics and a compact device size, the source region (24), the gate region (26) of the junction field effect transistor (36), and the base region (22) of the vertical bipolar transistor (34) are formed in a single well region (18) of a semiconductor substrate (10).

Abstract: A thin-film transistor having a thin-film channel region (20) inlaid in a recess (29) along the wall of a multi-layered insulating structure (14), and a gate electrode (12) electrically controlling current conduction in the thin-film channel (20) and separated therefrom by a gate dielectric layer (32). The multi-layered insulating structure (14) includes a spacing layer (28) which is withdrawn from the wall of the multi-layered insulating structure (14) and forms an inner wall of the recess (29). By residing in the recess (29), the thin-film channel region (20) is aligned to the multi-layered insulating structure (14) and the gate dielectric layer (32) separates exposed portions of the thin-film channel region (20) from the gate electrode (12). Thin-film source and drain regions (16, 18) are integral with the thin-film channel region (20) and are self-aligned to the multi-layered insulating structure (14).

Abstract: An EEPROM memory array includes a plurality of memory cells having a floating gate electrode (22) formed as a sidewall spacer adjacent to a control gate electrode (20). Source and drain regions (12, 14) reside in a semiconductor substrate (10) and define a segmented channel region (16) therebetween. A select gate electrode (18) overlies a first channel region (24) and separates the floating gate electrode (22) from the source region (12). The control gate electrode (20) overlies a third channel region (28) and separates the floating gate electrode (22) from the drain region (14). The floating gate electrode (22) overlies a second channel region (26) and is separated therefrom by a thin tunnel oxide layer (42). The EEPROM device of the invention can be programmed by either source side injection, or by Fowler-Nordheim tunneling. Additionally, a process is provided for the fabrication of an EEPROM array utilizing adjacent select gate electrodes (18, 18') as a doping mask.

Abstract: A method is provided for the formation of ultra-shallow boron doped regions in a semiconductor device. In one embodiment of the invention an N-type semiconductor substrate (15) is provided having a first P-type region formed therein. A dielectric layer (16) is formed on the substrate surface and a material layer (17) doped with fluorinated boron is formed on the dielectric layer (16). A second P-type region (22), characterized by a high dopant concentration at the substrate surface and a uniform junction profile, is formed in the substrate adjacent to the first P-type region by diffusing boron atoms from the material layer (17) through the dielectric layer (16) and into the substrate (15). The second P-type region (22) has a very shallow junction depth which is closer to the substrate surface than the first P-type region.

Abstract: A process for fabricating a high-reliability composite dielectric layer (19) includes the formation of a first oxynitride layer (14) on the surface (12) of a silicon substrate (10). The formation of the first oxynitride layer (14) is followed by an oxidation step to form a silicon dioxide layer (16) at the surface (12) of the substrate (10) and underlying the first oxynitride layer (14). The composite dielectric layer (19) is completed by exposing the substrate (10) to nitrous oxide, and diffusing a nitrogen bearing species through both the silicon dioxide layer (16) and the first oxynitride layer (14) to form a second oxynitride layer (18) underlying the silicon dioxide layer (16). The composite dielectric layer (19) exhibits a nitrogen-rich region at the interface between second oxynitride layer (18) and the silicon substrate (10). A second nitrogen rich region is also formed near the surface of the first oxynitride layer (14).

Abstract: An EEPROM device capable of operating with a single low-voltage power supply includes a control gate electrode (30) and a select gate electrode (14) overlying separate portions of a channel region (32). Electrical charge is stored in an ONO layer (20) overlying a portion of the channel region (32) and separating the control gate electrode (30) from the channel region (32). The memory device is programmed using source-side injection, where electrons traverse the channel region (32) and are injected into trapping sites (34) located within the silicon nitride layer (24) of the ONO layer (20). To provide the necessary field gradient within the channel region (32), the control gate electrode (30) is spaced apart from the source region (16) by the select gate electrode (14). In either of two embodiments, two layers of polysilicon are used to form the select gate electrode (14) and the control gate electrode (30). The second layer of polysilicon is formed as a sidewall spacer on the first layer of polysilicon.