Abstract: A semiconductor device having an overlapping memory cell (10), which includes a split wordline configuration and intersects at least a portion of the driver gate electrodes with each wordline. In one embodiment, a semiconductor substrate (11) has first and second active regions (13, 15) therein. A driver transistor (20) is formed in the semiconductor substrate (11), wherein the gate electrode (19) of the driver transistor (20) has a first portion overlying the second active region (15), a second portion extending beyond the first active region, and a third portion contacting the first active region (13). A wordline overlies (42) the second active region (15), wherein a first portion of the wordline forms the gate electrode of an access transistor (34) and a second portion of the wordline intersects the second portion of the driver transistor gate electrode (19) forming an overlap region (31).

Abstract: In one embodiment, a semiconductor memory cell (10) having a trench (24) and access transistor (54) formed in a well region (20). The trench (24) substantially contains an inverter (60) which is electrically coupled to ground and power signals by buried layers (12, 18) in the substrate (11). The inverter (60) has a toroidal, shared-gate electrode (40) which electrically controls a driver transistor (32) in the wall (26) of the trench (24), and a thin-film load transistor (42) in the central portion of the trench (24). A portion of the toroidal, shared gate electrode extends to an adjacent well region (20') and contacts well region (20') at cell node (13'). A ground signal is provided to load transistor (42) at the bottom surface (28) of the trench (42). A supply signal is provided by a buried layer (18) which is integral with driver transistor (32).

Abstract: A BiCMOS device and process are disclosed wherein the transistors components are fabricated on an SOI substrate. A SIMOX process is used to form a buried oxide layer in a single crystal silicon substrate followed by an epitaxial deposition to form a silicon body of varying thickness overlying the buried oxide layer. MOS transistors are then formed in a thin portion of the epitaxial layer and a vertical bipolar transistor is formed in the thick portion of the epitaxial layer.In accordance with one embodiment of the invention, a single crystal semiconductor substrate is provided having a principal surface and a buried oxide layer underlying the first surface. A lightly doped epitaxial layer of a first conductivity type having a thin MOS region and a thick bipolar region overlies the principal surface. A first and second isolation regions extending from the first surface to the buried oxide layer separate and electrically insulate the bipolar region from the MOS region.

Abstract: A method is provided for the formation of ultra-shallow boron doped regions in a semiconductor device. In one embodiment of the invention an N-type semiconductor substrate (15) is provided having a first P-type region formed therein. A dielectric layer (16) is formed on the substrate surface and a material layer (17) doped with fluorinated boron is formed on the dielectric layer (16). A second P-type region (22), characterized by a high dopant concentration at the substrate surface and a uniform junction profile, is formed in the substrate adjacent to the first P-type region by diffusing boron atoms from the material layer (17) through the dielectric layer (16) and into the substrate (15). The second P-type region (22) has a very shallow junction depth which is closer to the substrate surface than the first P-type region.

Abstract: A method for making a semiconductor device having an anhydrous ferroelectric thin film obtained from an anhydrous sol-gel solution. An anhydrous PZT sol-gel solution is prepared from Lead (II) Acetate Anhydrous which is thermally reacted with Zirconium and Titanium precursors to form a gel condensate. The sol-gel condensate is prepared without hydrolyzing the sol-gel solution to obtain precursor complexes which do not contain water. The formulation of the sol-gel exclusively by thermal condensation and in the absence of hydrolysis yields an anhydrous amorphous sol-gel having a uniform condensate composition. The anhydrous PZT thin film formed by the anhydrous sol-gel exhibits improved durability and substantially complete low-temperature conversion to the perovskite crystalline phase.

Abstract: A CMOS device and a method for its fabrication are disclosed. In one embodiment the CMOS device includes an NMOS transistor and a PMOS transistor each of which has silicided source and drain regions and a silicon gate electrode which includes a titanium nitride barrier layer. The NMOS transistor and PMOS transistors are coupled together by a silicon layer which is capped by a layer of titanium nitride barrier material. The source and drain regions are silicided with cobalt or other metal silicide which is prevented from reacting with the silicon gate electrode and interconnect by the presence of the titanium nitride barrier layer.

Abstract: A transistor is described having reduced series resistance and a reduced peak lateral electric field. The peak lateral field is reduced by forming an image charge in the surface of the substrate underlying the edges of the transistor gate electrode. The image charge is created by impregnating portions of an oxide layer overlying the source and drain regions with an impurity having the same conductivity as that of the underlying substrate. The depletion region formed in the substrate by the image charge provides a graduated electric filed in the channel preventing hot carrier injection into the gate oxide and increasing the breakdown voltage. The image charge is of an opposite conductivity to that of the substrate and is thus composed of minority carriers. The high concentration of majority carriers near the surface of the substrate lower the series resistance of the transistor thereby increasing the drive current.

Abstract: An etching process for the patterning of electrodes and a ferroelectric dielectric layer in a ferroelectric capacitor, which is formed in a semiconductor device, is disclosed. A series of overlying layers including a first electrode layer (16), a ferroelectric layer (18), and a second electrode layer (20) are etched to form a ferroelectric capacitor (14) on a semiconductor substrate (10). The second electrode layer (20) is selectively etched in a first aqueous solution containing hydrochloric acid, nitric acid, and a metal etching compound comprised of phosphoric acid, nitric acid, and acetic acid. The ferroelectric layer (18) is selectively etched in a second aqueous solution containing hydrogen peroxide, hydrofluoric acid, and nitric acid. The etch rate of the ferroelectric layer in the second aqueous solution is controlled by selection of the relative concentration of the chemicals used to form the solution.

Abstract: A method for patterning a conductive metal oxide film on a substrate surface by means of an oxygen plasma etching process. In one embodiment, a substrate (10) is provided having a ruthenium oxide layer (14) overlying a dielectric layer (12). The substrate is placed on an electrode (24) positioned in a vacuum chamber (20) and the vacuum chamber is evacuated to a low pressure. Oxygen gas is introduced to the vacuum chamber and RF power is applied to form an oxygen plasma within the vacuum chamber. The oxygen plasma preferentially etches the ruthenium oxide layer (14) and does not etch the underlying dielectric layer (12). The oxygen plasma etching process can be used to form high resolution ruthenium oxide features during semiconductor device fabrication of ferroelectric capacitors (60) and other electronic components.

Abstract: A semiconductor device having a thin-film transistor (22) and a process for making the device. The semiconductor device includes a substrate (11) having a principal surface. A gate electrode (29) overlies the principal surface and a gate dielectric layer (23) overlies the gate electrode (29). A conductive channel interface layer (25) overlies the upper surface of the gate electrode (29) and is spaced apart from the gate electrode (29) by the gate dielectric layer (23). A conductive thin-film layer (57) overlies the gate electrode (29) and forms a metallurgical contact to the channel interface layer (25). Remaining portions of the thin-film overlie the principal surface and form source and drain regions (63, 65) of the thin-film transistor (22). The thin-film source and drain regions (63, 65) are formed by placing a diffusion barrier cap (60) over the channel portion (61) of the thin-film layer (57) and introducing conductivity determining dopant into the thin-film layer (57).

Abstract: A method is provided for forming a material layer in a semiconductor device using liquid phase deposition. A material layer such as a metal layer, a dielectric layer, a semiconductor layer or a superconducting layer is deposited by the liquid-phase thermal decomposition of a metal-organic precursor dissolved in an anhydrous organic solvent. The organic solvent has a chemical polarity corresponding to the selected metal-organic precursor and has a normal boiling point above the decomposition temperature of the selected precursor. As a result of few restrictions on the range of precursor physical properties, the present invention enables the use of a wide variety of molecular compositions which can be used for the formation of an equally wide variety of material layers. In one embodiment of the invention, a semiconductor substrate is subjected to a liquid mixture comprising a metal-substituted heterocyclic acetylacetonate precursor dissolved in tetradecane (b.p. 254.degree.C.).

Abstract: An insulated gate field effect transistor having a vertically layered elevated source/drain structure includes an electrically conductive suppression region for resistance to hot carrier injection. The device includes a semiconductor substrate of first conductivity type having a gate insulator disposed on the surface of that substrate. A gate electrode, in turn, is disposed on the gate insulator. A lightly doped drain region of second conductivity type is formed in the substrate in alignment with the gate electrode. An electrically conductive suppression region having a first low electrical conductivity is positioned to electrically contact the drain region, but is electrically isolated from the gate electrode and is spaced a first distance from the gate electrode. A heavily doped drain contact also contacts the drain region and is spaced further away from the gate electrode than is the electrically conducted suppression region.

Abstract: An improved semiconductor device interconnect comprising a conductive layer (30) with an underlying diffusion barrier metal (26) is attached to a doped glass layer (20) by an intermediate metal adhesion layer (22). The metal adhesion layer (22) is deposited onto the doped glass layer (30) prior to the formation of contact openings (24) in the doped glass layer (30) and the subsequent formation of the interconnect metallization. In one embodiment, a titanium diffusion barrier (26) is deposited onto a doped glass layer (30) having an aluminum metal adhesion layer (22) thereon and contact openings (24) therethrough. The titanium is annealed to form a silicide (28) in a substrate region (14) exposed by the contact opening (24) and an aluminum interconnect (32) is formed contacting the silicide region (28).

Abstract: A semiconductor device is disclosed having an electronic component mounted to a mounting surface opposite a heat transfer surface of a die support member. The electronic component includes a plurality of bonding pads each electrically coupled to a plurality of package leads by a number of inner leads. A package body encloses the electronic component, the inner leads, the proximal ends of the package leads and the mounting surface of the die support member. The package body includes an opening exposing a portion of the heat transfer surface of the die support member. An insertable thermally conductive heat sink extends into the opening in the package body making thermal contact with the heat transfer surface of the die support member. A thermally conductive electrically insulating adhesive joins the heat sink to the package body securing the heat sink to the package body. In the assembly process, the package body is formed prior to attachment of the heat sink.

Abstract: A semiconductor device (10) having first and second wiring layers (30, 33) on opposite surfaces of a carrier substrate (12) interconnected through vias (32) formed in the carrier substrate (12) electrically coupling an electronic component (18) to a mounting substrate through compliant solder balls (26) displaced away from vias (32), the semiconductor device (10) characterized by a standard size carrier substrate (12) having high performance electrical package interconnections (24) and good heat dissipation. Improved electrical performance is obtained by providing independent wiring layers (30, 33) each having a lead trace layout specifically designed for a particular electronic component (18) and a particular board connection requirement while using a standard size package outline. Assembly costs are reduced by providing a plastic package mold (36) over a standard size carrier substrate (12) capable of supporting a variety of different electronic components (18) themselves having varying dimensions.

Abstract: A BiCMOS device and process are disclosed wherein the transistors components are fabricated on an SOI substrate. A SIMOX process is used to form a buried oxide layer in a single crystal silicon substrate followed by an epitaxial deposition to form a silicon body of varying thickness overlying the buried oxide layer. MOS transistors are then formed in a thin portion of the epitaxial layer and a vertical bipolar transistor is formed in the thick portion of the epitaxial layer. In accordance with one embodiment of the invention, a single crystal semiconductor substrate is provided having a principal surface and a buried oxide layer underlying the first surface. A lightly doped epitaxial layer of a first conductivity type having a thin MOS region and a thick bipolar region overlies the principal surface. A first and second isolation regions extending from the first surface to the buried oxide layer separate and electrically insulate the bipolar region from the MOS region.

Abstract: A process for fabricating isolation regions in a semiconductor substrate which does not depend upon pattern definition capability. In one embodiment a device isolation region (30) is formed in a semiconductor substrate (12) by first creating a trench (18) in the substrate (12). A single-crystal SiGe layer (24) is formed to overlie the wall surface (20) of the trench (18). A layer of selectively-deposited, single-crystal silicon (26) is formed in the trench (18) using both the bottom surface (22) of the trench (18) and the SiGe layer (24) as a nucleation site for the selective deposition process. After the single-crystal silicon layer (26) is formed, the SiGe layer (24) is selectively removed and the previously occupied space is filled with a dielectric material to form isolation region (30).

Abstract: A semiconductor device and process wherein an ITLDD device (60) is formed having an inverse-T (IT) transistor gate with a variable work function (.PHI.) across the gate. The variable work function is attained by depositing a work function adjusting layer onto the thin gate extensions of the IT-gate. In accordance with one embodiment of the invention, a semiconductor substrate (10) of a first conductivity type is provided having a gate dielectric layer (12) formed thereon. First and second lightly doped regions (36, 37) of a second conductivity type are formed in the substrate which are spaced apart by a channel region (38). An IT-gate electrode (48) is formed on the gate dielectric layer overlying the first and second lightly doped regions and the channel region. The IT-gate has a relatively thick central section (32) and relatively thin lateral extensions (50) projecting from the central portion along the gate dielectric layer.

Abstract: Adjacent buried contacts (11, 12, 13) formed at the principal surface of a well or substrate region (14) of a semiconductor device, each having a doped contact region (29, 30 31) of one conductivity type and a punch-through prevention region (36, 37, 38) of the opposite conductivity type surrounding the lower portion of the doped contact region are provided. The punch-through prevention region may advantageously be of the same conductivity type as the substrate. By performing an extra implant or other impurity introduction step while the mask to etch the contacts through the dielectric layer remains in place, the procedure to provide punch-through protected buried contacts may be easily integrated into current processes without the need for an extra mask. Such a structure and procedure enables buried contacts to be spaced closely together without over-doping the well region (14) in which source-drain regions (40, 42, 44, 46) are also formed thus avoiding a degradation in device performance.

Abstract: A trench is formed in a substrate and lined with a dielectric. A first silicon layer of a first conductivity is deposited in the trench. A second silicon layer of a second conductivity type is deposited over the first layer and a third silicon layer of the first conductivity type is deposited on the second layer, all are disposed within the trench area. A second trench is then formed through the third and second layers and into the first layer. The second trench is then lined with a dielectric and filled with a gate polysilicon. The appropriate connections are then made to the gate, the third layer, and the substrate.