Abstract: In a field programmable gate array, a test circuit for testing the signal path of a line, through a pass gate, and onto a second line. A memory cell outputs at a V.sub.GG level, where V.sub.GG .gtoreq.V.sub.DD +V.sub.TN. In order to dynamically test the signal path, three transistors and two test signals are used to apply either 0 volts or V.sub.GG to control the pass gate. Two of the transistors are coupled to the memory cell and the pass gate, whereas the third transistor is coupled to the first and second transistors and ground. The two test signals and an inverter control these transistors so that the memory state can be changed to dynamically switch the pass gate according to the test configuration. An electrical signal is then sent through the signal path under test, and the result is monitored.

Abstract: A two-transistor flash EPROM cell for high-speed high-density PLD applications is provided. The two-transistor cell includes a storage transistor connected in series to an access transistor. The storage transistor prevents problems associated with both over-erase and punch-through, and allows for scaling of the gate length to realize 5V cell programming.

Abstract: A programmable logic device (PLD) performs a self-test blank check erase verify operation on memory elements of the PLD to verify that they are erased prior to programming. An enhanced reference voltage source is provided to reliably generate a reference source voltage at a predetermined voltage level regardless of variations in the on-chip power supply voltage and temperature variations. The reference voltage source includes a first resistor connected between the on-chip voltage source and an output node, a second resistor connected to the output node, and a reference voltage adjustment circuit connected between the second resistor and ground. The reference voltage adjustment circuit is programmable to selectively connect the output node to ground through one or more resistive elements in response to input signals such that the output node is maintained at the predetermined reference voltage.

Abstract: A memory cell array includes a first memory cell, a second memory cell, and a bit line which extends between the first and second memory cells. During normal operation, the bit line is used as a write path for data values to be written to the first and second memory cells. If the first memory cell is defective, the bit line is used to route the data value stored in the second memory cell to the first memory cell, effectively replacing the first memory cell with the second memory cell. In another embodiment, a memory cell array includes a first memory cell for storing a first data value and a second memory cell for storing a second data value. A first pair of bit lines are coupled to the first memory cell, and the first data value is written to the first memory cell on the first pair of bit lines. A second pair of bit lines are coupled to the second memory cell, and the second data value is written to the second memory cell on the second pair of bit lines.

Abstract: A composable memory array for a programmable logic device includes a plurality of dedicated, serially coupled memory tiles. Each memory tile includes a plurality of dual-port memory cells, each having a first port and a second port, a plurality of first bit lines coupled to the first ports and a plurality of second data lines coupled to the second ports. The first and second bit lines extend across memory tiles. Each memory tile includes a plurality of first configuration circuits which allow the first bit lines of the memory tile to be coupled to the first bit lines of the previous memory tile. Thus, any number of consecutive memory tiles can be concatenated to form a memory array using the first set of bit lines. Non-consecutive memory tiles include a plurality of second configuration circuits which allow the second bit lines of the memory tile to be coupled to the second bit lines of a previous memory tile.

Abstract: An electrical connection arrangement for a programmable integrated circuit is provided. An electrical device is disposed proximate to a vertical longline which is used for transporting address and data signals. The electrical device includes a vertical address line extending from the device. A horizontally arranged interconnection line is electrically connected to the vertical address line extending from the device. Furthermore, the horizontally arranged interconnection line is programmably connectable to the vertical longline. By electrically hardwire connecting the horizontally arranged interconnection line to the vertical address line extending from the device, only one programmable interconnect point is required to transfer signals from the vertical longline into the electrical device itself. Thus, impedance is reduced, while addressing speed is improved. Also, by adding additional horizontal interconnect lines, the present invention reduces routing barriers.

Abstract: A pass gate circuit includes a pass transistor and a body bias control circuit for biasing the body of the pass transistor to reduce body effect. The body bias control circuit includes one or more control transistors arranged to selectively connect the substrate (body) of the pass transistor to the drain or gate of the pass transistor when predetermined voltages are applied to the drain and gate of the pass transistor. As a result, the pass transistor exhibits a reduced body effect in the on-state. In one embodiment, the body bias control circuit includes a first control transistor having a drain and gate connected to the gate of the pass transistor, a gate connected to the drain of the pass transistor, and a source. The body bias control circuit also includes a second control transistor having a drain connected to the source of the first control transistor, a source connected to a body of the pass transistor, and a gate connected to the drain of the pass transistor.

Abstract: Signal routing resource tiles that can be manipulated as circuit "cells" in that they can be readily characterized and implemented on a programmable logic device, e.g., a field programmable gate array (FPGA). In one embodiment, vertical placement and horizontal placement routing resource tiles are provided. Routing resources tiles may be selectively added in areas of the programmable logic device determined to be prone to high signal congestion, e.g., the central portions of the array, and along the array perimeter. The additional routing resource tiles simplify routing for complex logic functions and increase utilization of configurable logic blocks (CLBs) forming the array. The tiles can be positioned within the array in any position horizontally or vertically within the CLB array. Specifically, placement can be either in the core of the chip or along the periphery with each tile providing programmable connections to the existing routing resources (e.g., input/output ports) within the CLBs.

Abstract: A memory system having a single-sided memory cell, a first voltage supply terminal and a control circuit is provided. The single-sided memory cell has a first node and a second node. Data values are written to the memory cell by selectively applying data signals to the first node or the second node, and data values are read from the memory cell from the second node. The control circuit is coupled to receive a data signal having one of a first state and a second state. The control circuit couples the first node of the memory cell to the first voltage supply terminal when the data signal is in the first state, thereby writing a first data value to the memory cell. The control circuit couples the second node of the memory cell to the first voltage supply terminal when the data signal is in the second state, thereby writing a second data value to the memory cell.

Abstract: A mixed mode RAM/ROM cell includes a volatile memory cell and an antifuse coupled to the cell. In an array of mixed mode memory cells, addressing circuitry is coupled to the volatile memory cells and programming circuitry is coupled to the antifuses. After an antifuse is programmed, the associated memory cell is transformed from a volatile memory to a non-volatile memory. Specifically, during normal operation, a standard supply voltage is provided to all antifuses. Thus, after a power down or power fluctuation, the programmed antifuses ensure subsequent configuration of their respective volatile memory cells.

Abstract: A configuration emulation circuit generates configuration signals to emulate a Programmable Logic Device (PLD) in a configuration timing relationship and a configuration protocol relationship between a programming circuit and the PLD. The circuit includes a first circuit to emulate the PLD in the configuration timing relationship. The circuit also includes a second circuit to emulate the PLD in the configuration protocol relationship. The second circuit is coupled to receive a configuration mode signal and is responsive to the configuration mode signal.

Abstract: A flash electrically erasable programmable read only memory (EEPROM) cell fabricated in a semiconductor substrate. A first well region having a first conductivity type is located in the semiconductor substrate. A second well region having a second conductivity type, opposite the first conductivity type, is located in the first well region. A non-volatile memory transistor and an independently controllable access transistor are fabricated in the second well region. The non-volatile memory transistor and the access transistor are connected in series, such that the source of the access transistor is coupled to the drain of the non-volatile memory transistor.

Abstract: An antifuse is described that can be formed without masks or mask steps beyond those required for a conventional CMOS process. The antifuse includes adjacent p-type and n-type diffusion regions that together form a P-N junction. The diffusion regions are tapered toward one another such that the P-N junction is located at a necked-down region of the antifuse. The diffusion regions are connected to respective terminals of a programming-voltage source via first and second metal electrical contacts, typically of aluminum metal. Each of the first and second electrical contacts includes a point directed toward the other of the first and second electrical contacts. The antifuse is programmed by providing a reverse-bias programming voltage across the electrical contacts. This programming voltage exceeds the breakdown voltage of the P-N junction so that current flows through the necked-down region of the antifuse between the points on the respective first and second electrical contacts.

Abstract: A multiplexer chain is coupled to two logic gates which in turn propagate their respective output signals in different directions, thereby providing bidirectional signal distribution. The output lines of multiple multiplexer chains are combined together using a logic gate chain to create a bus line with a larger number of drivers while substantially maintaining switching speed and flexibility in routability. In one embodiment, two OR chains propagate signals in opposite directions. The top OR chain combines the outputs of all the multiplexer chains to its left. Similarly, the bottom OR chain combines the outputs of all the multiplexer chains to its right. The output of the entire bus is provided at both the leftmost and the rightmost end of the OR chain. The bus output is also provided at tap points by combining the outputs of the top logic gate chain and the bottom logic gate chain using a logic gate.

Abstract: A programmable logic cell which includes a first transistor having a first conductivity type, and a second transistor having a second conductivity type, opposite the first conductivity type. The first transistor is coupled in series between a first voltage supply terminal and an output terminal, while the second transistor is coupled in series between a second voltage supply terminal and the output terminal. The first and second transistors share a common floating gate and a common control gate, which extends over the common floating gate. The floating gate has substantially the same layout as the control gate. When the floating gate is programmed to store charge of a first polarity, the programmable logic cell enters a non-volatile first state and provides an output signal having a first logic state. When the floating gate is programmed to store charge of a second polarity, the programmable logic cell enters a non-volatile second state and provides an output signal having a second logic state.

Abstract: A programmable logic array improves connectivity and more efficiently routes signals between logic blocks by allowing programmable connections between each logic block and the horizontal interconnect lines above and below the logic block. Thus, more efficient signal transfer is achieved, particularly when connectivity is required between logic blocks in adjacent rows. The logic array decreases transmission delay and frees up bandwidth on vertical interconnect lines, thereby optimizing the use of routing resources.

Abstract: A plurality of DRAM cells are used to store the state of the programmable points in a programmable logical device (e.g., a field programmable gate array or FPGA). An individual DRAM cell is used in conjunction with each programmable interconnect point (PIP) within the FPGA to hold a logical state indicating the connectivity state of the PIP. During a refresh cycle, each DRAM memory cell is loaded with its current logical state in order to maintain this state within the PIP. An information store contains duplicate data for each DRAM cell and this duplicate data is supplied and read during the refresh cycle in order to provide each DRAM cell with its proper logical state. In this manner, the refresh cycle does not alter the logic configuration of its associated FPGA DRAM cell.

Abstract: A programmable bidirectional interconnect circuit selectively provides either a buffered connection, a non-buffered connection, or a disconnection (tristate mode). The circuit includes six transistors coupled to a buffer and two signal lines.

Abstract: An apparatus for loading configuration information into a programmable integrated circuit (e.g., an FPGA) configurable to perform parallel loading or bit serial loading within the same architecture. The configuration information is presented to the FPGA in data frames of N serial bits each. Each data frame is divided into discrete serial portions having Y bits each (e.g., a data frame comprises N/Y portions). In parallel mode, the portions are loaded into a segmented configuration register, one portion per programming cycle, such that Y bits are loaded into the segmented configuration register in parallel. On each programming clock cycle during parallel loading, all the bits of a data frame portion are simultaneously loaded into the segments of the configuration register (at the first bit position for each segment) such that each segment receives one bit per programming cycle. The bits of the configuration register are then shifted down by one and the cycle repeats for the next data frame portion.

Abstract: The present invention provides an efficient programming verification system for Programmable Logic Devices (PLDs). Based upon IEEE JTAG standard boundary scan test architecture, the invention provides a novel test architecture including a configuration register and a signature analyzer coupled between the TDI and TDO pins of the JTAG architecture. The configuration register of the invention comprises three parts: an address register/counter, a data register, a status register. The address register/counter performs dual functions depending upon an instruction received by an instruction register. The invention eliminates the need to load each address sequentially into the address register/counter for programming by enabling the address register/counter to auto-increment the address for memory locations. After loading an initial address value, the address register/counter automatically increments the address for programming memory cells.