Abstract: A communication system has stations arranged in clusters of member stations, each of which communicates with the other member stations. One member station is a head station of the cluster that communicates with head stations of other clusters. The stations are configured by determining the communication state between a station and one or more cluster head stations. The station is assigned to at least one cluster when a prescribed communication state has been determined between the station and the cluster head station. The station is set to be in independent communication with the one or more cluster head stations which have the prescribed communication state with the station.

Abstract: An intelligent telephone network provides personalized communication services based on a voice identification of the subscriber. The network executes a speech processing operation to identify the person or a party that the person is calling as a known subscriber. The network can provide personalized services to several subscribers sharing a common line. For incoming calls to such a line, the network executes an interactive procedure to determine from the caller which subscriber is being called. If the line is free, the switch applies distinctive ringing. If the line is in use, the switching office uses the profile of the identified subscriber to provide a distinctive call waiting tone or a voice message over the line. The tone or voice message indicates to the party using the line that there is a call waiting and specifically identifies the called subscriber.

Abstract: There is disclosed multiple embodiments of a predictive active compensation system for dampening vibration in an optimum manner employing feedback control wherein stiffness of dampening material is adjusted on a continuous and dynamic basis to ensure that relative displacement between vibrating machine or object and its foundation does not exceed particular limits including limits preventing impact between object and foundation. In these disclosed systems and methodologies of the present invention the foundation may also be subjected to movement. Further disclosed are computer plots of mathematical models on which embodiments of the present invention are based, thereby demonstrating efficacy of the present invention.

Abstract: A disk array subsystem for use in a data processing system. In one embodiment, the disk array subsystem comprises a generally rectangular chassis having a top wall, a bottom wall, a pair of side walls, an open front end and an open rear end. Disposed within the chassis are three power supplies, a pair of controller boards, a backplane, and a set of twenty disk drive modules. A mounting structure comprising four first disk drive module guide plates and a pair of second disk drive module guides is fixedly mounted within the chassis for removably mounting the disk drive modules in the chassis through the open front end and for placing the disk drive modules in approximate alignment with the backplane for electrical connection therewith. Each first guide plate is shaped to include five parallel slotted channels, and each second disk drive module guide plate is shaped to include ten parallel grooves.

Abstract: A data processing system is disclosed in which a plurality of high performance, intelligent, mass storage input-output devices are linked to a host controller by an input-output interface bus which is divided into three sections. Each section is completely independent of the other two sections and used for a different and specific purpose. One section is used to transfer commands and retrieve status information. A second section is used to handle device requests for data transfer and device signals for operation complete. The third section is used to transfer data to and from a device. Since the three sections are completely independent, simultaneous transfer of command control and data to different input-output devices or to a single input-output device can be performed.

Abstract: Methods are set forth which provide for the allocation of bandwidth for point-to-point, serial, bidirectional communication paths in a digital switching system. Bandwidth allocation is performed at both ends of a path (e.g. T1 line, IML, etc.) and may take place in either direction. Furthermore, according to the preferred embodiment of the invention, the Bandwidth Allocation Facility (BAF) at each end of a given path allocates bandwidth in integer multiples of maximum switching system granularity. The BAF also supports the implementation of user requests for any one of a plurality of allocation and boundary rules. To minimize the probability of contention and out of band signalling between the BAF pair associated with a given path, a front-to-back search mechanism is assigned for one BAF of the pair, while the other BAF utilizes a back-to-front search mechanism.

Abstract: Methods and apparatus are set forth for quickly making switched virtual connections (SVCs) in a digital circuit switch that integrates voice and data using common switch, control and distribution equipment. SVCs provide concurrent data connection service from one station device, such as a PC, to other station devices over a single line for each station device where the line may also carry voice and terminal data service. A switch control processor remembers connection requests from station devices and acts on opportunities to utilize available bandwidth in an optimal manner. Dynamic connection reconfiguration techniques allow the system to "scavenge" bandwidth unused by voice or terminal data traffic for SVCs thereby providing the largest possible data rate at any given time. Short signalling messages and indexed values are used in order to speed activation time for previously defined connections while resource allocation is performed by the switch control processor to further enhance system operating speed.

Abstract: An integrated office controller (IOC) network includes, in combination, a plurality of station devices each capable of transmitting and receiving multiplexed bearer and signal channel information; user port interface means for carrying said multiplexed information between a station device and a station multiplex/demultiplex device (SMX); a plurality of SMXs, each associated with and coupled to a predefined cluster of said station devices, via said user port interface means, for concentrating the multiplexed information froms said interface means into channel signals, central equipment module (CEM) means, including a call processor, a non-blocking switch matrix and clock means, for switching channel signals through said switch matrix under the control of said cell processor and clock means; transmission system means, capable of interfacing SMXs and trunk cards to said CEM, where said transmission system means includes modular line interface module (LIM) means for interfacing a plurality of SMXs and the CEM, an

Abstract: Methods and apparatus are set forth which improved the sub-rate channel carrying capacity and the efficiency of bandwidth usage, over the CCITT I.463 standard, for switching systems having a switching "granularity", defined as the smallest channel size that can be switched through the system, of better then 64 Kbps (e.g. a switching system that can switch 8 Kbps fragments). These methods and apparatus are capable of performing rate adaptation for multiple synchronized subrate channels in accordance with a predefined multiplexing protocol. The protocol calls for "time interleaved" multiplexed rate adaptation to be performed, i.e., multiple sub-rate channel data is packaged into fragment size envelopes (or integer multiples thereof). The width of a fragment is also matched (ideally equal) to the granularity of the system's switch.

Abstract: A data processing system having a local memory bus, a main memory coupled to the local memory bus and a host central processing unit coupled to the local memory bus includes a single input/output controller for interfacing a plurality of input/output devices to the local memory bus. The input/output controller includes a plurality of input/output device controllers, each input/output device controller being adapted to be connected to at least one input/output device, a single microprocessor for managing the overall operations of the input/output controller, a single buffer memory for storing a program of instructions for the microprocessor and temporarily storing data received from the input/output devices and a gate array for interfacing all of the input/output device controllers to the local memory bus.

Abstract: Methods and apparatus are set forth that perform Format Conversion between bit streams which embed sub-rate circuit data according to different protocols. The invention (1) locates and extracts the sub-rate circuit data embedded, in an input serial bit stream, in accordance with a first predefined protocol (2) aligns the data in a buffer, and (3) creates an output bit stream in which the extracted circuit data is reformatted and inserted in accordance with a second predefined protocol. A programmable bit map driven format conversion module operates the data aligned in the aforementioned buffer. The conversion process is bidirectional and, in one embodiment of the invention, facilitates conversion between a single stage time division multiplexed data format and a two stage time division multiplexed format (e.g. X.50 and I.463) by utilizing the aforesaid bit map driven format conversion technique.

Abstract: Methods and apparatus are set forth which improve the efficiency of bandwidth usage over the CCITT I.463 standard, for switching systems having a granularity of better then 64 Kbps (e.g. 8 Kbps). Furthermore, methods and apparatus are set forth which are capable of performing rate adaptation for synchronized sub-rate channels in a manner geared to package sub-rate data in fragment size envelopes (or integer multiples thereof), where the width of a fragment is matched (ideally equal) to the granularity of the system's switch. This improves the efficiency of the rate adaptation process and maximizes the use of the system's switching and bandwidth capacity.

Abstract: Methods and apparatus are set forth which provide for the allocation of bandwidth for point-to-point, serial, bidirectional communication paths in a digital switching system. Bandwidth allocation is performed at both ends of a path (e.g. T1 line, IML, etc.) and may take place in either direction. Furthermore, according to the preferred embodiment of the invention, the Bandwidth Allocation Facility (BAF) at each end of a given path allocates bandwidth in integer multiples of maximum switching system granularity. The BAF also supports the implementation of user requests for any one of a plurality of allocation and boundry rules. To minimize the probability of contention and out of band signalling between the BAF pair associated with a given path, a front-to-back search mechanism is assigned for one BAF of the pair, while the other BAF utilizes a back-to-front search mechanism.

Abstract: A data processing system in which the interface for connecting a host controller to a burst multiplexor channel comprises two sections one to handle the transfer of data and the other to handle the transfer of command and status information. The interface also includes logic to monitor the division of any transfer into bursts and logic to arbitrate for the two sections for any given burst.

Abstract: A communications network comprising nodes interconnected by communication lines employs a method of allocating data rates to fragments of line bandwidth which facilitates efficient allocation of available line bandwidth. Each node maintains, for each communication line connected to it, a bit map means having a bit position associated with each fragment available in the line for keeping track of which fragments are available and which are in use. Identification of available bandwidth fragments in the line is then accomplished by finding appropriate bit values in the bit map means; fragments allocated are marked in the bit map means. A node thus need not allocate fragments contiguously, and available bandwidth is equally allocable by either of the two nodes interconnected by a particular line.

Abstract: An implantable pump, actuated by the patient in whom the pump is implanted, to provide pain relief and/or other therapeutic benefits. There is disclosed a fully implantable pump system, including a reservoir for holding fluid, a septum by which the reservoir is periodically refilled, and a resilient pump chamber responsive to manual pressure, for delivering limited amounts of the fluid through a catheter to a specific location within the body of the patient. Alternative embodiments disclosed include designs incorporating "windkessel-like" devices for controlling discharge of the fluid to the specific location to occur over extended time periods at relatively constant flow rates.

Abstract: A data processing system which includes a central processing unit (CPU) to which is connected an I/O bus and a memory bus is disclosed. The data processing system further includes an I/O controller and a video control section. The I/O controller includes a terminal control section which is connected to the CPU through an RS232 Cable, an I/O control section which is connected to the I/O bus over a single line and a single processor for managing both the terminal control section and the I/O control section. The I/O control section includes a plurality of interface and control subsystems each for use with a separate peripheral device and an I/O bus interface and control subsystem. The terminal control section includes a video control section interface through which data is sent directly to the video control section over a separate line, and a keyboard interface for interfacing the terminal control section to a keyboard.

Abstract: A portable computer is sized to fit into a businessman's attache case and may be seated on a surface for use in either a normal position or a tilted forward position. The portable computer includes a housing having a base, a front top cover, a rear top cover and a foot door. The front top cover is pivotally attached to the front of the rear top cover and the rear top cover is fixedly attached to the base. Computer electronics (i.e. printed circuit boards), and two floppy disk drives are mounted inside the housing on the base at the rear and a full size keyboard is mounted inside the housing on the base at the front. A battery pack is disposed in the rear top cover of the housing. A full size liquid crystal display monitor is mounted on the front top cover. The foot door is movably mounted on the back of the base. When the front top cover is pivoted open the display screen is viewable and the keyboard is accessible.

Abstract: An input/output (I/O) device controller for a data processing which is implemented on a single printed circuit board, includes a terminal control section, an I/O control section, a processor section and a timing generator section. The terminal control section includes a keyboard interface, an RS232 interface for transmitting and receiving data from the system host CPU over an RS232 line, and a video control section interface. The I/O control section includes a plurality of different I/O interface and control units for connecting the section to a number of different I/O devices and a system I/O bus interface and control unit for interfacing the section to the system I/O bus. The processor section manages the operations of the terminal control section as well as the I/O control section.

Abstract: A video control section for a data processing system for controlling a CRT display is disclosed. The video control section includes a video memory comprising an array of dual port RAMS which is connected through an interface to the system memory bus, a shifter, a palette, a D/A converter, an oscillator section, a timing and synchronizer section and a microprocessor. The microprocessor, which is connected to the system memory bus through an interface, manages the overall operations of the video control section to generate video signals for the CRT display and in addition along with the oscillator section and timing and synchronizer section generates all of the video timing and control signals for the CRT display.