Abstract: An optical mirror mount for use in mounting an optical mirror in a generally upright position on a horizontal supporting surface and which is adjustable in pitch and yaw is disclosed. The mount includes a bracket having a horizontal leg and a vertical leg. The horizontal leg is affixed to the supporting surface by a pair of mounting screws, one of the mounting screws extending through a circular mounting hole at one end of the horizontal leg into a threaded hole in the supporting surface and the other mounting screw extending through an elongated mounting slot at the other end of the horizontal leg into another threaded hole in the supporting surface. The vertical leg includes an upper section onto which the optical mirror is attached and a lower section, the upper section being bendable relative to the lower section.

Abstract: A computer network is disclosed in which a plurality of computer stations are interconnected by a single bus and wherein access to the bus is controlled by the computer stations themselves through an adapter unit at each station. Each adapter unit is assigned a unique number. When the network is running normally, control of the bus is continually passed from one live adapter unit to another in numerical sequence and the bus is active with messages, control signals or status signals from the particular adapter unit that happens to be in control at the time. If, for any reason, there should be no activity on the bus for a preselected time interval, all adapter units detecting this condition enter an election mode to elect from amongst themselves one adapter unit to assume control and resume activity. In the election mode, each participating adapter unit sends a pulse out over the bus and then monitors the bus for activity for a time period directly proportional to its assigned number.

Abstract: Microinstruction selection circuitry effects the selection of successive microinstructions of a sequence. Current and next PCs are stored in first and second registers. Current PC is provided to a memory from one register to fetch a current instruction from memory while a next PC is generated and stored in the other register. At end of a current instruction, next PC becomes current PC and a new next PC is generated and stored in the register previously storing the former current PC.

Abstract: Apparatus for monitoring and/or controlling the operations of a computer at a user site from a support center over a telephone line, the computer at the user site including a central processing unit (CPU) and a display terminal. The apparatus includes a telephone instrument at each location connected to the telephone line, a display terminal connected to an acoustic coupler at the support center and a control and switching device at the user site connected to the CPU, to the display terminal at the user site and to an acoustic coupler. When a link is established between the acoustic coupler at the support center and the acoustic coupler at the user site over the telephone line, the display terminal at the support center is operable with the display terminal at the user site in either an on-line mode or a conversational mode. In the on-line mode, either display terminal can input to the CPU and the output from the CPU is displayed at both display terminals.

Abstract: A computer system architecture includes a processor for processing data, a memory for storing at least macroinstructions for use by the processor, microinstruction logic for storing and providing sequences of frequently used microinstructions, and busses for transmitting at least macroinstructions between the processor and memory. Microinstruction memory circuitry stores microinstructions in segmented form in available microinstruction memory space. Microinstruction segment by segment selection circuitry effects the selection of successive microinstructions of sequences of microinstructions.

Abstract: A controller for interfacing a central processor unit (CPU) to a peripheral storage device which can be tested for proper operation independent of the peripheral storage device includes a sequencer, a buffer, a microprocessor and various error detection logic. A gate is coupled between the sequencer and the input of the peripheral storage device for enabling or disabling the transfer of data from the sequencer to the peripheral storage device and a multiplexer is coupled between the microprocessor, the output of the peripheral storage device and the sequencer for selecting inputs to the sequencer from either the microprocessor or the peripheral storage device. During a normal write operation, write signals are sent from the CPU to the sequencer through the buffer and then from the sequencer to the peripheral storage device through the gate.

Abstract: An improved wire matrix ballistic impact printhead apparatus including a plurality of engaging structures for maintaining the armatures of a like plurality of electromagnetic actuators in proper positional alignment with the associated print style, for allowing individual adjustment of armatures to optimize printhead operation, for preloading the armatures with a force that will return them to their original position after the printing operation, and for damping vibrations at printhead operating frequencies.

Abstract: Therein is disclosed high speed digital computer system architecture. System architecture includes a processor for processing machine language digital data and a memory for storing at least machine language instructions for use by the processor. Instructions or data are transmitted between memory and processor by memory input and output busses. Signals are transmitted between computer system and external devices by I/O apparatus. Instruction pre-fetch circuitry is disclosed for fetching from memory, and storing, instructions in advance of instructions being executed by the processor. Also disclosed are a high speed memory and memory input and output busses providing high memory bus bandwidth and simple memory bus interface circuitry. Processor circuitry is disclosed for allowing high speed initiation and execution of instruction sequences. I/O circuitry is disclosed which allows I/O apparatus to easily adapt to a variety of external devices or to changes in computer machine language or instructions.

Abstract: Memory control circuitry is disclosed for providing memory refresh during battery back-up operation. Memory addressing circuitry is connected between circuitry, such as a processor, providing memory refresh addresses, and memory addressing inputs. During normal main power supply operation, refresh addresses are provided to the memory from the processor. Upon occurrence of a main power supply failure, and start of battery back-up operation, the last refresh address provided by the processor is stored in the memory addressing circuitry and successively incremented to provide refresh addresses to the memory .

Abstract: A laser recording system is disclosed in which a beam of light from a laser is split into first and second beams. The first beam is modulated with digital signals from a computer and deflected by a rotating mirror onto the surface of a photoconductive drum. The second beam is deflected by the rotating mirror onto a curved timing plate. The surface of the timing plate is provided with a series of unevenly spaced reflective markings representative of evenly spaced spot positions on the surface of the drum. Light reflected by the timing plate as the second beam scans its surface and strikes the reflective markings impinges on a photodetector located at the center of curvature of the timing plate and is converted by the photodetector into a corresponding series of electrical signals.

Abstract: An improved method of fabricating metal-semiconductor interfaces such as Schottky barriers and ohmic contacts. There is disclosed apparatus and method (or process) for chemically converting, etching, or passivating the surface of a material, such as the surface of a silicon wafer, in a gaseous plasma environment consisting of atomic, neutral nitrogen which causes the surface of the material to be resistant to otherwise subsequent nascent surface oxide buildup. This process is particularly useful in manufacture of Schottky diodes, transistors, and other electronic components or discrete and integrated devices requiring high quality metal-semiconductor junctions or interfaces.

Abstract: An open loop, stepper-motor-driven, rigid magnetic disc memory apparatus for use with a data processing system. A rigid magnetic disc with high track density is driven by a stepper motor in an open-loop fashion or without servomechanism control.

Abstract: A Floating Point Processor or Floating Point Unit (FPU) with capability for performing exponent/sign-related calculations concurrently with mantissa-related calculations. The operation of the FPU within the context of a general purpose digital computer system is shown. The FPU has control, mantissa, and exponent/sign functional blocks which have unique architectural arrangements and interconnections therebetween, and also have interfacing structure for connecting system control and clock signals to the control block. The operation of the FPU is timed in a particular manner to permit its operation to be transparent to, or to not impact operation of the CPU, when the FPU communicates with main memory or the CPU.

Abstract: A data processing system which employs a CPU and a MOS memory, the memory requiring replenishing or refreshing periodically. The CPU includes microcode containing microinstructions, the microinstructions providing control for the CPU including control for the memory. The refreshing scheme employs apparatus for decoding of these microinstructions and for providing refreshing signals to the memory in such a manner that all non-refreshing operations of the data processing system proceed without being delayed by operation of the refreshing apparatus. The algorithm which guides the operation of the CPU includes a number of system operating modes (such as FETCH, MULTIPLY, DIVIDE, HALT, DATA CHANNEL, and others). These modes each contain an operating state designated RAC.fwdarw.MEM which indicates that a refresh signal automatically is forwarded to the MOS memory when a particular operating mode runs through its respective operating states.

Abstract: A microprogrammed processor having a versatile hardware and data path configuration in which control signals for data paths, the ALU function, the shifter and all other control signals are derived from the current microprogram control word which is normally periodically clocked into a ROM buffer. Included are capabilities for effective addressing, incrementing the program counter and computer instruction skips, all while the instruction register is being loaded from memory by direct connection of selected bits of the memory bus to the ROM buffer to derive a micro-instruction. Also included is a conditional skip condition allowing the processor to skip the next instruction by testing selected bits of the instruction register which manipulates the micro-code for this purpose. Another capability is that of hardware structuring to readily accommodate WCS. Other capabilities provide for bit and byte manipulation, allowing the micro-instruction to readily load constants into the ALU, and for marking purposes.

Abstract: An open loop, stepper-motor-driven, rigid magnetic disc memory apparatus for use with a data processing system. A rigid magnetic disc with high track density is driven by a stepper motor in an open-loop fashion or without servomechanism control.

Abstract: A rigid magnetic disc memory apparatus for use with a data processing system. A magnetic read/write head is accurately positioned parallel and adjacent to the plane of a rigid magnetic disc with high track density by a stepper motor in an open-loop fashion without servomechanism control.

Abstract: There is disclosed a circuit for providing a comparison signal representing phase relationship between a clock pulse train and a variable rate input pulse train. The comparison signal can be used to synchronize clock and input pulse trains. The circuit includes a phase difference measuring circuit providing a first signal proportional to phase difference between input pulse train and clock pulse train, the signal having related discontinuities at the points of minimum and maximum phase difference between input and clock pulse trains. A second signal is generated representing a selected value of phase difference, the selected value being greater than the minimum phase difference and less than the maximum phase difference. First and second signals are then compared to provide a signal representing difference between the measured and selected values of phase difference.

Abstract: An open loop, stepper-motor-driven, rigid magnetic disc memory apparatus for use with a data processing system. A rigid magnetic disc with high track density is driven by a stepper motor in an open-loop fashion or without servomechanism control.

Abstract: An open loop, stepper-motor-driven, rigid magnetic disc memory apparatus for use with a data processing system. A rigid magnetic disc with high track density is driven by a stepper motor in an open-loop fashion or without servomechanism control.