Abstract: An open loop, stepper-motor-driven, rigid magnetic disc memory apparatus for use with a data processing system. A rigid magnetic disc with high track density is driven by a stepper motor in an open-loop fashion or without servomechanism control.

Abstract: An open loop, stepper-motor driven, rigid magnetic disc memory apparatus for use with a data processing system. A rigid magnetic disc with high track density is driven by a stepper motor in an open-loop fashion or without servomechanism control.

Abstract: An open loop, stepper-motor-driven, rigid magnetic disc memory apparatus for use with a data processing system. A rigid magnetic disc with high track density is driven by a stepper motor in an open-loop fashion or without servomechanism control.

Abstract: A line power cord voltage-magnitude adaptor is described herein. In a particular embodiment of the present invention, the power plug, line cord, and adaptor plug are pre-assembled as one component of the electrical equipment system; various voltage requirements can thus be prepared-for, whereby the equipment need not be altered, regardless of the eventual market for the equipment. The present invention can be used with virtually all kinds of electrical equipment energized by AC power, including computer systems.

Abstract: There is disclosed a data processing system which employs parallel processors (PP's or P--P's) that are interfaced to the CPU, and which derive their control from microinstructions stored in an extension to the CPU microcode structure. This extension forms part of the CPU/PP interface. The P--P's increase speed of operation of the data processing system in which they are employed by operating synchronously and simultaneously with the CPU when called upon by CPU microcode structure to execute particular algorithms.

Abstract: A single-chip memory-sense amplifier for a data processing system. There is disclosed a sense amplifier (level converter) and bus driver for use in a data processing system, to receive signal inputs from main memory and to drive a memory bus connecting output of the sense amplifier to the CPU. This sense amplifier is intended for use with memory fabricated from N-channel MOS technology. The circuitry of the sense amplifier is fabricated from bi-polar technology and formed on a single monolithic integrated circuit chip. The biasing scheme employed within the circuitry of the sense amplifier provides reliable operation, by making the amplifier relatively insensitive to power supply variations.

Abstract: At least one parallel processor (PP or P-P) is connected between a central processing unit (CPU) interface and main memory for processing certain data simultaneously and synchronously with operation of the CPU. Integrated circuit apparatus for implementing the functions performed by the PP includes an arithmetic and logic unit (ALU), a set of registers, microprogrammable circuitry (RAM's, ROM's, PROM's) and other integrated circuitry. The PP includes decode and control apparatus, which decodes microinstructions stored in an extension to the control store of the CPU, the extension forming part of the CPU/P-P interface, and thereafter employs the decoded microinstructions to control operation of the P-P.

Abstract: A method of reading on a record medium a two level code representing at least one character of a set of characters, each character having six consecutive transitional occurrences between the two levels of the code comprising: scanning the record medium to derive a time based electrical signal representative of said transitional occurrences; measuring four periods between alternate ones of said transitional occurrences; comparing each two overlapping periods to generate three ratios, each ratio representing not more than one of three possible values of nearly one, smaller than one and larger than one, and; decoding the values arrived at for said three ratios to define a character. The arrangement of the coded indicia on the record medium or the font of type for imprinting the same is such that, for each character, not more than two bits of the same level are arranged consecutively and two consecutive bits of a first level are not immediately followed by two consecutive bits of a second level.

Abstract: An improved plasma etching process. There is disclosed apparatus and method (or process) for etching patterns in metal films deposited on a semiconductor wafer. This improved process is particularly useful in the fabrication of certain semiconductor devices, such as MOS and bipolar integrated circuits and Schottky transistors (semiconductor/metal interfaces) which employ contact "fingers". The fingers are constructed from layers of metal, such as aluminum, tungsten, and titanium with aluminum being the outermost layer.

Abstract: An improved method of fabricating metal-semiconductor interfaces such as Schottky barriers and ohmic contacts. There is disclosed apparatus and method (or process) for chemically converting, etching, or passivating the surface of a material, such as the surface of a silicon wafer, in a gaseous plasma environment consisting of atomic, neutral nitrogen which causes the surface of the material to be resistant to otherwise subsequent nascent surface oxide buildup. This process is particularly useful in manufacture of Schottky diodes, transistors, and other electronic components or discrete and integrated devices requiring high quality metal-semiconductor junctions or interfaces.

Abstract: There is disclosed an input/output system, employed within a data processing system that includes a central processing unit (CPU). The CPU includes improved input/output shift register structure of interfacing structure for interfacing with I/O structure. The I/O structure includes improved CPU transceiver and peripheral device transceiver apparatus. The device transceiver interfaces with an improved device controller. In the preferred embodiment of the present invention, the CPU, CPU transceiver, device transceiver, and device controller, all being constructed primarily from MOS technology, are each contained within a respective chip. Further features of the input/output system include capability for placement of multiple transceiver/controllers and their respective peripheral devices at varying distances from the CPU by virtue of novel clock and data transmission means which maintains accurate processing of data regardless of propagation delay, distortion, data skewing, etc.

Abstract: There is disclosed an input/output system, employed within a data processing system that includes a central processing unit (CPU). The CPU includes improved input/output shift register structure or apparatus for interfacing with an I/O bus (bus structure). The I/O structure includes improved CPU transceiver and peripheral device transceiver apparatus. The device transceiver interfaces with an improved device controller. In the preferred embodiment of the present invention, the CPU, CPU transceiver, device transceiver, and device controller, all being constructed primarily from MOS technology, are each contained within a respective chip. Further features of the input/output system include capability for placement of multiple transceiver/controllers and their respective peripheral devices at varying distances from the CPU by virtue of novel clock and data transmission means which maintains accurate processing of data regardless of propagation delay, distortion, data skewing, etc.

Abstract: A microprogrammed processor in which control signals for data paths, the ALU function, the shifter and all other control signals are derived from the current microprogram control word which is normally periodically clocked into a ROM buffer. The processor provides for microbranching capability with and/or without a test, testing capabilities including direct addressing with simultaneous temporary address storage capability for future recall, and selective testing of computer instruction bits for decoding to address the next micro-instruction. Additional capabilities provide for flexible access to the micro-code instruction control store through a ROM address multiplexer which allows for selection of at least one of four possible micro-instruction addresses determined by micro-code control decode logic.

Abstract: There is disclosed an input/output system, employed within a data processing system that includes a central processing unit (CPU). The CPU includes improved input/output shift register structure or interfacing means for interfacing with I/O means (bus structure). The I/O means includes improved CPU transceiver and peripheral device transceiver apparatus. The device transceiver interfaces with an improved device controller. In the preferred embodiment of the present invention, the CPU, CPU transceiver, device transceiver, and device controller, all being constructed primarily from MOS technology, are each contained within a respective chip. Further features of the input/output system include capability for placement of multiple transceiver/controllers and their respective peripheral devices at varying distances from the CPU by virtue of novel clock and data transmission means which maintains accurate processing of data regardless of propagation delay, distortion, data skewing, etc.

Abstract: There is disclosed an MOS pulse-edge detector circuit. In certain applications it is desirable or necessary for an MOS switching circuit to respond substantially simultaneously to an edge of a control pulse. The present invention relates to a novel MOS component design which utilizes inherent or intrinsic capacitance thereof in a manner to detect and respond to an edge of a pulse such as a control or clock pulse at the time of occurrence of that edge.

Abstract: The present invention relates to an improved MOS memory structure. There is disclosed an array of memory cells of the three-device-per-bit type, the array being formed in rows and columns. Temporary storage cells are disclosed which are employed to receive and temporarily store inverted digital information from selected memory cells responsive to a READ signal. The inverted digital information is re-inverted upon restoration thereof into the selected memory cells, thus eliminating any need of accounting for the polarity or status of the data, whereby propagation delay time through the memory structure is reduced.

Abstract: A microprogrammed processor having a versatile hardware and data path configuration in which control signals for data paths, the ALU function, the shifter and all other control signals are derived from the current microprogram control word which is normally periodically clocked into a ROM buffer. Included are capabilities for effective addressing, incrementing the program counter and computer instruction skips, all while the instruction register is being loaded from memory by direct connection of selected bits of the memory bus to the ROM buffer to derive a micro-instruction. Also included is a conditional skip condition allowing the processor to skip the next instruction by testing selected bits of the instruction register which manipulates the micro-code for this purpose. Another capability is that of hardware structuring to readily accommodate WCS. Other capabilities provide for bit and byte manipulation, allowing the micro-instruction to readily load constants into the ALU, and for marking purposes.

Abstract: A method of reading on a record medium a two level code representing at least one character of a set of characters, each character having six consecutive transitional occurrences between the two levels of the code comprising: scanning the record medium to derive a time based electrical signal representative of said transitional occurrences; measuring four periods between alternate ones of said transitional occurrences; comparing each two overlapping periods to generate three ratios, each ratio representing not more than one of three possible values of nearly one, smaller than one and larger than one, and; decoding the values arrived at for said three ratios to define a character. The arrangement of the coded indicia on the record medium or the font of type for imprinting the same is such that, for each character, not more than two bits of the same level are arranged consecutively and two consecutive bits of a first level are not immediately followed by two consecutive bits of a second level.

Abstract: A hand-operated scanner having an inverted T-shaped extension for slideably receiving two adjacent fingers for manipulating the scanner and simultaneously allowing the operator's fingers to remain free for merchandise packaging, merchandise check-out and/or making keyboard entries by artful placement of the extension in relation to the scanner reading head.