Abstract: Encachement apparatus consisting of a first cache, a second cache connected to the first cache, registers for storing data, an adder receiving inputs from a first multiplexer connected to the first cache and a second multiplexer connected to the second cache and to the registers, and control apparatus connected to the first cache, the first multiplexer, and the second multiplexer. The first cache outputs a cache entry in response to a key. The cache entry contains a first displacement value, a base specifier specifying either one of the registers or the second cache, and in the case of entries specifying the second cache, a second displacement value. The first displacement value is output to the first multiplexer, the base specifier is output to the control apparatus, and the second displacement, if present, is output to the second cache.

Abstract: Encachement apparatus consisting of a first cache, a second cache connected to the first cache, registers for storing data, an adder receiving inputs from a first multiplexer connected to the first cache and a second multiplexer connected to the second cache and to the registers, and control apparatus connected to the first cache, the first multiplexer, and the second multiplexer. The first cache outputs a cache entry in response to a key. The cache entry contains a first displacement value, a base specifier specifying either one of the registers or the second cache, and in the case of entries specifying the second cache, a second displacement value. The first displacement value is output to the first multiplexer, the base specifier is output to the control apparatus, and the second displacement, if present, is output to the second cache.

Abstract: Encachement apparatus consisting of a first cache, a second cache connected to the first cache, registers for storing data, an adder receiving inputs from a first multiplexer connected to the first cache and a second multiplexer connected to the second cache and to the registers, and control apparatus connected to the first cache, the first multiplexer, and the second multiplexer. The first cache outputs a cache entry in response to a key. The cache entry contains a first displacement value, a base specifier specifying either one of the registers or the second cache, and in the case of entries specifying the second cache, a second displacement value. The first displacement value is output to the first multiplexer, the base specifier is output to the control apparatus, and the second displacement, if present, is output to the second cache.

Abstract: Encachement apparatus consisting of a first cache, a second cache connected to the first cache, registers for storing data, an adder receiving inputs from a first multiplexer connected to the first cache and a second multiplexer connected to the second cache and to the registers, and control apparatus connected to the first cache, the first multiplexer, and the second multiplexer. The first cache outputs a cache entry in response to a key. The cache entry contains a first displacement value, a base specifier specifying either one of the registers or the second cache, and in the case of entries specifying the second cache, a second displacement value. The first displacement value is output to the first multiplexer, the base specifier is output to the control apparatus, and the second displacement, if present, is output to the second cache.

Abstract: A system for modifying the manner in which a processor in a digital computer system responds to operation codes in certain instructions. All instructions to which the system responds have operation code syllables containing an operation code and an operation code modifier. In instructions having certain operation codes, the operation code modifier contains a value which modifies the manner in which the processor responds to the operation code. When the processor receives an instruction having such an operation code, a part of the processor which is responsive to the operation code modifier employs the value in the operation code modifier to modify the interpretation of the instruction by the processor. The manner in which the value is employed depends on the operation code. Several uses of the operation code modifier are disclosed.

Abstract: Therein is disclosed high speed digital computer system architecture. System architecture includes a processor for processing machine language digital data and a memory for storing at least machine language instructions for use by the processor. Instructions or data are transmitted between memory and processor by memory input and output busses. Signals are transmitted between computer system and external devices by I/O apparatus. Instruction pre-fetch circuitry is disclosed for fetching from memory, and storing, instructions in advance of instructions being executed by the processor. Also disclosed are a high speed memory and memory input and output busses providing high memory bus bandwidth and simple memory bus interface circuitry. Processor circuitry is disclosed for allowing high speed initiation and execution of instruction sequences. I/O circuitry is disclosed which allows I/O apparatus to easily adapt to a variety of external devices or to changes in computer machine language or instructions.

Abstract: A computer network is disclosed in which a plurality of computer stations are interconnected by a single bi-directional bus and wherein access to the bus is controlled by the computer stations themselves through an adapter unit at each station. Each adapter unit includes a microcontroller, a transmitter, a receiver, a send buffer, a receive buffer, a line activity indicator, a pulse producing device, a read circuit and a write circuit. Each adapter unit has a unique assigned number. When the network is running and stable, control of the bus is continually passed from one live adapter unit to another in numerical sequence according to its unique assigned number and the bus is active with messages, control signals or status signals separated by relatively short intervals. If only one adapter unit is live, control is continually passed to itself.

Abstract: Systems and method for resolving unresolved pointers in digital computer systems. In unresolved pointers, addresses are represented by means of data items from which the addresses may be derived. The unresolved pointer is resolved when the represented address is derived from the data items. One such system includes the unresolved pointers and procedures for resolving the unresolved pointers in the digital computer system's memory and apparatus in the digital computer system's process which operates under control of pointer translation microcode to translate pointers into represented addreses and under control of call-return microcode for invoking procedures from microcode. The pointer translation microcode responds to an unresolved pointer by causing the call-return microcode to invoke the procedures for resolving the unresolved pointer. Using the data items in the unresolved pointer, the procedures derive the represented address and return it to the pointer translation microcode.

Abstract: The processor of the present invention executes procedures, which comprise S-language instructions and names. S-languages are of higher order than typical machine languages and can be tailored to user high-order languages. Each procedure includes a dialect code which the processor interprets, enabling it to execute any of a plurality of dialects of S-languages. The processor includes means for resolving names into operand logical addresses. The processor possosses multiple levels of microcode control means, each with its own set of stacks.

Abstract: An improved system for performing call and return operations in a computer system in which every call and return operation changes the program counter and the frame pointer but some call and return operations change other state. Included in the state which may change in the computer system of the present invention is addresses used in calculating other addresses, an identifier specifying which instruction set the processor is executing, and protection state which determines what data may be accessed during execution of a procedure. In the system, the state saved and restored in the call and return operations is divided into basic state saved and restored on every call and return and extended state saved and restored on only some calls and returns. The frame associated with an execution accordingly contains either saved basic state or saved basic state and saved extended state.

Abstract: Improved apparatus for specifying and computing the current length of varying-length data items, together with methods for computing the current length. The apparatus and methods are used in a digital computer system wherein data items are represented by names associated with name table entry items in memory. The name table entry associated with the name represented by the varying-length data item includes a current number of elements item specifier specifying the address of a current number of elements item which specifies the number of elements currently in the represented varying-length data item. The name table entry further includes an element size specifier specifying the size of the elements. A name processor in the processor uses the current number of elements item specifier to obtain the the address of the current number of elements item and and fetches the current number of elements item from memory.

Abstract: In the digital computer system of the present invention, data items called immediate names represent other data items. The immediate name specifies either the address of the represented data item or the address of a pointer to the represented data item. Each immediate name contains a base address specifier specifying one of a set of architectural base addresses, an indirection specifier specifying whether the immediate name specifies the address of the represented item or the address of a pointer to the item, and a displacement from the specified architectural base address. The architectural base addresses are contained in registers accessible to a processor in the digital data processing system. The registers are loaded only when the processor preforms a call operation or a return operation.

Abstract: Therein is disclosed high speed digital computer system architecture. System architecture includes a processor for processing machine language digital data and a memory for storing at least machine language instructions for use by the processor. Instructions or data are transmitted between memory and processor by memory input and output busses. Signals are transmitted between computer system and external devices by I/O apparatus. Instruction pre-fetch circuitry is disclosed for fetching from memory, and storing, instructions in advance of instructions being executed by the processor. Also disclosed are a high speed memory and memory input and output busses providing high memory bus bandwidth and simple memory bus interface circuitry. Processor circuitry is disclosed for allowing high speed initiation and execution of instruction sequences. I/O circuitry is disclosed which allows I/O apparatus to easily adapt to a variety of external devices or to changes in computer machine language or instructions.

Abstract: Improved apparatus for computing locations in compound data items and current lengths in varying-length compound data items when the elements in the compound data items and the varying-length data items have sizes which are powers of 2. The apparatus is used in a digital computer system wherein data items are represented by names associated with name table entry items in memory. The digital computer system's processor includes a name translator for calculating addresses and lengths using the name table entries associated with names. The name table entry associated with a name representing a compound data item or varying-length compound data item having elements whose size is an integer power of 2 includes an element size specifier which has as its value the exponent specifying the power of 2 equal to the size of the elements.

Abstract: An improved system for saving state during a call operation and restoring state during a return operation in a computer system in which different call and return operations require the saving and restoring of different amounts of state. The components of the system are call instructions whose operation codes specify the amount of state to be saved, frames which contain either basic state saved on every call operation and restored on every return operation or basic state and extended state saved only on certain calls and returns, a frame type item in each frame which specifies whether it contains only basic state or both basic and extended state, a single return instruction, state-saving apparatus which is responsive to the different call instructions, and state-restoring apparatus which is resposive to the single return instruction and to the frame type item.

Abstract: A computer network is disclosed in which a plurality of computer work stations are interconnected for interstation communications by a single electrically continuous bi-directional bus. Each computer work station includes a data processing device and a transceiver. The transceiver includes a receiver section for receiving signals transmitted over the bus and a transmitter section for transmitting signals onto the bus. The receiver section is coupled to the input of the data processing device by a first optical isolator and the transmitter section is coupled to the output of the data processing device by a second optical isolator. The data processing device and the first optical isolator are powered by a first power supply which is connected and grounded to the AC mains while the transceiver and second optical isolator are powered by a second power supply which is connected to the neutral conductor on the bus and is floating.

Abstract: Improved apparatus for specifying and resolving addresses of operands in a digital data processing system. Instructions executed by the system are contained in procedures. Addresses are calculated using a set of architectural base addresses. Operands are represented in the instructions by means of names. The names include immediate names, which directly specify one of the architectural base registers and a displacement, and table names, which specify a name table entry in a name table associated with the procedure. The name table entry specifies how the address of the operand represented by the table name may be derived using the architectural base addresses and information contained in the name table. Each name table entry includes a basic name table entry. The basic name table entry contains a base source specifier and a base or displacement specifier.

Abstract: A diagnostic display terminal system for remotely troubleshooting hardware, software and operational malfunctions in a computer over telephone lines includes a user-site diagnostic display terminal assembly and a support-site diagnostic display terminal assembly. Each diagnostic display terminal assembly includes a microprocessor controlled display terminal, a telephone instrument and a split baud rate modem, the modem serving to interface the display terminal and the telephone instrument to a telephone line. The system provides alternate voice and data communication between the user-site and the support-site and permits almost instantaneous change-over between voice and data. The telephone link effectively merges the two display terminals together in that each display terminal can monitor the actions of the other and that each display terminal can run all programs executable at the user-site display terminal.

Abstract: An apparatus and method are disclosed for testing the faces of a polygon mirror for angular inclination and flatness while the polygon mirror is rotating at its intended operating speed. The apparatus includes an autocollimator for making the test readings, a strobe light for supplying light in the form of pulses to the autocollimator and a control mechanism including a laser, a light detector, a counter and a momentary contact switch for controlling the timing of the light pulses emitted by the strobe light so that the faces of the polygon mirror can be tested, one face at a time. The apparatus further includes a fiber optic probe which illuminates a unique number imprinted on the face illuminated through the autocollimator with light pulses directly from the strobe light so that the face that is being illuminated can be identified.

Abstract: A phase-locked loop circuit is disclosed for use, for example, in the data recovery system of a rotating magnetic disk drive unit employing a phase encoded signal format. The phase-locked loop circuit has a dual mode of operation wherein captive range is assured by providing a first frequency locking mode of operation wherein a voltage controlled oscillator (VCO) is first locked in frequency to a reference signal and a second phase locking mode of operation wherein the VCO is subsequently locked in phase to an MFM signal independently of the frequency assumed by the latter signal. In addition to the VCO, the phase-locked loop circuit includes a frequency detector, a phase detector, a filter, an amplifier, a pair of frequency dividers, a pulse shaping network and a plurality of switches. A potentiometer is coupled to the input of the amplifier and is used to supply a voltage signal to the amplifier which is sized to offset system phase errors caused by the various components in the phase-locked loop circuit.