Abstract: A control and switching device which is installed at a customer's computer (local) site and which links a remote terminal by modems over telephone lines to the system console, the TTO/TTI port and the ALM/IAC port of the host computer, and to a user terminal for remote diagnosis of hardware and software problems is disclosed. The device, which is coupled by separate lines to the modem at the local site, the system console, the user terminal the TTO/TTI port and the ALM/IAC port of the host computer includes a microprocessor a memory, various logic and control circuits and a three position keyswitch. The keyswitch provides a first level of security and limits the type of access allowed by a remote caller. When the switch is in a first position, the caller has no access to the host system. When the switch is in a second position, the remote caller can connect to the ALM/IAC port or communicate with the user terminal but cannot change configuration data.

Abstract: A control and switching device which links a remote terminal by modems over telephone lines to a local central processing unit (CPU) and a local computer console terminal is disclosed. The device, which is coupled by separate lines to the modem at the local site, the local console and the TTY and ASYNC ports of the CPU, includes a microprocessor, a memory, logic circuits and a switch assembly. The switch assembly includes first, second and third switches which are interlocked and which allow three different levels of remote access of the remote terminal. When the first switch is depressed, the device is powered down, the remote terminal has no access to either the TTY or ASYNC ports of the CPU and the local console is hardwired through the device to the TTY port of the CPU. When the second switch is depressed, the local console is hardwired to the TTY port of the CPU and the remote terminal is electrically connected to the ASYNC port of the CPU.

Abstract: Programmable feature card circuitry includes: a signal processor with parallel input/output (I/O) data ports and responsive to command of the PBX call processor, signal memory, and a signal interface for converting the PBX signal format to a processor compatible format; the signal memory including program memory for storing signal processor program signals representing the programmed algorithm to be performed by the signal processor in the execution of the user selected PBX support function and including data memory for storing data signals from the PBX, the signal processor executing the stored programmed algorithm in response to the command signals from the PBX call processor.

Abstract: A floating-point unit constructed of at least two identical modules. Each module contains registers for storing floating-point data, a sign and exponent processing unit for processing the sign and exponent portions of floating-point values, and a mantissa processing unit for processing the mantissa portion. Buses allow transfer of operands from the registers to the mantissa and sign and exponent processing units and the return of the result to the registers. Interconnections between the modules and configuration logic on each module enable the modules to function as a single floating-point unit. The interconnections include connections between corresponding buses of the modules and connections between corresponding mantissa processing units. The configuration logic is responsive to position signals indicating the module's position relative to other modules in the floating-point unit and precision signals indicating the precision of the floating-point data being processed by the unit.

Abstract: An integrated digital network (IDN) includes a matrix and user signal ports for exchanging voice, data, IDN control, and building control digital signals between the matrix and user equipment, the digital signals comprising single samples of each signal type from each user port in each IDN sample time interval, the IDN further including a transmission system for concentrating user port digital signal samples of each sample time interval, by common signal type, into multiple bit channel signals for exchange between the user ports and matrix signal ports of the matrix switch, the matrix switch interconnecting each channel signal from one or more user ports to one or more other user ports.

Abstract: Method and apparatus for improving instruction decoding in a microcode-controlled digital computer system. The microinstruction sequences are made simple and compact enough that sufficient complexity is required in the instruction decoding logic that it is feasible to custom-configure a gate array to perform instruction decoding. The resultant gate array, by virtue of being embodied in a single integrated circuit, is extremely fast and compact and has low power requirements.

Abstract: A data processing system having separate kernel, vertical and horizontal microcode, separate loading of vertical microcode and a permanently resident kernel microcode, and a soft console with dual levels of capability. The system includes a processor having dual ALC and microcode processors, and an instruction processor. Also included are a processor incorporating a multifunction processor memory, a malfunction nibble shifter, and a high speed look-aside memory control.

Abstract: A data processing system having separate kernel, vertical and horizontal microcode, separate loading of vertical microcode and a permanently resident kernel microcode, and a soft console with dual levels of capability. The system includes a processor having dual ALC and microcode processors, and an instruction processor. Also included are a processor incorporating a multifunction processor memory, a multifunction nibble shifter, and a high speed look-aside memory control. Adaptive microcode control means 272 are disclosed in which microinstruction sequencing is a function 273 of the current microinstruction and current machine state.

Abstract: A data processing uses instructions which may refer to operands in main memory by either physical or logical addresses. The central processor has an internal memory organized as two portions. The first portion provides a scratchpad memory function for the central processor and the second portion is responsive to logical addresses to provide corresponding physical addresses.

Abstract: A content-addressable memory module which performs an associative clear operation in response to a clear signal provided on a clear line. The associative clear operation simultaneously clears all registers in the content-addressable memory module whose contents match bits in a pattern input to the content-addressable memory module. A mask input along with the pattern determines which bits of the pattern are significant for the match. Each register in the content-addressable memory module has a bidirectional match line associated with it. A register's bidirectional match line carries a match signal only if that register contains data matching the pattern bits specified by the mask and the bidirectional match line is receiving a match signal from an external source. Clearing logic associated with each register clears the register when a clear signal appears on the clear line while the register's bidirectional match line is carrying a match signal.

Abstract: A digital computer system in which data storage is referred to by a descriptor comprising an object number denoting a variable-length block of storage, an offset indicating how far into that block a desired data item begins, and a length field denoting the length of the desired data item. Separate means exist for manipulating each of the three descriptor portions, thus facilitating repetitive operations on related or contiguous operands. Various levels of microcode control are included. Each level of microcode control has its own stack, facilitating interrupts between levels. Stacks are duplicated in "secure stacks" in memory to protect against loss of state data from the stacks.

Abstract: A digital data system having a memory with a unique multi-ported memory I/O means. Separate means are provided for communicating with any of several buses. Address information, operands, instructions and Input/Output data may be separately sent and received over various of the buses.

Abstract: A digital computer system in which data operands are represented by names. Each procedure includes a name table, and means are provided to employ the name table to resolve the names into storage addresses at run time. The system also has the ability to run any of a plurality of S-Languages (an S-Language being conceptually similar to a machine language but of higher order); each S-Language can be optimally tailored to a high-order user language. Each procedure includes a dialect code which indicates the dialect of S-Language to which the instructions in the current procedure belong, and the system has provision to execute each procedure accordingly.

Abstract: A digital computer system in which the memory is structured into objects, which are blocks of storage of arbitrary length, in which the data items are accessed by specifying the desired object and the desired data item's offset into that object. The memory controls accommodate any number of memory arrays of any size, automatically transforming the addresses to present the appearance of a single unified memory bank.

Abstract: Apparatus and methods for the calculation of addresses of data items in digital computer systems which perform call and return operations. In the digital computer systems of the invention, items of data called immediate names represent other items of data and specify how the address of the represented item is to be calculated. Certain immediate names represent items of data whose addresses are calculated using linkage pointers. Such an immediate name specifies the linkage pointer to be used in the calculation. Linkage pointers are pointers whose values remain unchanged during an execution of a procedure. When the digital computer system's processor executes the call operation, the processor places the addresses represented by the linkage pointers in internal registers.

Abstract: A digital computer uses a memory which is structured into objects, which are blocks of storage of arbitrary length, in which data items are accessed by descriptors which for a desired data item specify the object, the offset into that object, and the length of the data object. The computer system of the present invention further provides the ability to execute any of a plurality of dialects of internal instructions, the repertoire of such dialects being virtually infinite, since there is the ability to load a supporting microcode during operation as needed.

Abstract: A method for executing call and return instructions in a digital computer system operating under control of microcode. The microcode may specify calls to and returns from sequences of microinstructions. A call microinstruction sequence corresponds to the call instruction. The call microcode in turn calls other microinstruction sequences for deriving pointers representing the location of the called procedure and of arguments from operands in the call instruction. As the call microcode obtains each argument pointer, it places the pointer on the stack. After it has obtained all of the argument pointers, it passes the pointer to the called procedure and a pointer to the argument pointers to a general call microinstruction sequence. That microinstruction sequence locates the called procedure, makes a new frame including the argument pointers, and saves the state necessary to resume execution of the call microinstruction sequence itself.

Abstract: An intelligent asynchronous controller (IAC) for use in operably coupling a plurality of asynchronous input/output (I/O) devices to a host central processing unit (CPU) is disclosed. The IAC is designed and programmed to control the transfer of data between the plurality of I/O devices and the CPU, to perform character processing on the data received from the I/O devices before transmission to the host CPU and to perform other types of data processing.

Abstract: A system for performing operations on data items in digital computer systems in which the instructions may not specify internal registers in the processor as destinations of data received from memory or sources of data provided to memory. The system includes a result memory, apparatus for executing operations, instructions containing operation codes which specify that the result memory is to be a source of data to be operated on by the apparatus for executing operations, and control apparatus responsive to the operation codes for controlling the apparatus for executing operations. The result memory stores only the results of previous operations and may serve only as an input to the apparatus for executing instructions. The apparatus for executing operations may receive items to be operated on from either the computer system memory or the result memory.

Abstract: A digital data bus system operating asynchronously with a fixed clock and having a automatically variable data rate selected by sending and receiving units. A master clock is generated by a master controller and distributed to one or more peripheral controllers of the data bus system through a single clock line. In addition to address/data lines, a single handshake hold signal is shared by the master and all peripheral controllers. All data transfers are executed on a bus clock pulse and data transfer rate is controlled by the sending and receiving units through operation of the hold signal. A receiving unit not ready to receive information on the bus will assert hold signal on hold signal line and the transmitting unit will maintain the information presently on the bus during each clock period in of which hold signal is asserted. Data transfer is executed on next clock pulse after termination of hold signal.