Abstract: A method for decoding a Manchester-II encoded DISPLAYPORT compatible signal is provided. In this method, several counters are reset. A unit interval (UI) counter is incremented for each UI received upon receipt of a valid UI, and the value of the UI counter is compared to a plurality of threshold values after the UI counter is incremented. When the value of the UI counter exceeds each of the threshold values, for each clock cycle, a sum counter is incremented corresponding to the exceeded threshold value, and a plurality of window lengths are calculated, where each window is calculated based at least in part on the value of one of the sum counters at predetermined values of the UI counter.

Abstract: A phase-locked loop (PLL) circuit includes a reference clock divider with a reference clock input, a phase-frequency detector, a charge pump, a loop filter, a voltage controlled oscillator and a feedback divider. A method of operating the PLL circuit comprises the steps of detecting a failure of a reference clock applied to the reference clock input, disabling the charge pump upon detection of a reference clock failure, monitoring the reference clock to detect restoration of a regular reference clock, upon detection of a regular reference clock, detecting occurrence of the next pulse from the feedback divider, and enabling the charge pump upon detection of the next pulse from the feedback divider.

Abstract: Methods and apparatus to test and compensate multi-channel digital-to-analog converters (DACs) are described. In some examples, a multi-channel digital-to-analog converter (DAC) and an error detector are implemented in an integrated circuit. The multi-channel DAC includes a first DAC channel configured to generate a first analog representation of a digital input signal, and a second DAC channel configured to generate a second analog representation of the digital input signal. The error detector is configured to compare the first analog representation and the second analog representation to generate a difference signal, and to output a signal indicative of whether the difference signal is greater than a predetermined threshold.

Abstract: A synchronous rectifier is switched in accordance with a primary switch transition and a reference signal representing current in a current storage device to which the synchronous rectifier is coupled. A current emulator provides a signal representing current in the current storage device as a volt-second product so that current stored in the current storage device while the primary switch is on is discharged by the synchronous rectifier. The use of a current emulator provides an inexpensive solution for controlling synchronous rectifier transitions without resorting to more expensive current sensing solutions that are commercially impracticable. Blanking intervals are provided for avoiding false transitions of the synchronous rectifier when the primary switch turns on and after the synchronous rectifier turns off. The disclosed system and method can be applied to flyback converters for a synchronous rectifier on the secondary side of a transformer, or the inductor of buck converters.

Abstract: A circuit board (CB) and method for automatic testing of an electronic device under test (DUT). The circuit board (CB) has a first terminal (T1) for coupling to automatic test equipment (ATE) including a first signal generator (SG1), a second terminal (T2) for coupling to the device under test (DUT), a circuit path (W1) interconnecting the first and second terminals (T1, T2), and a PIN (Positive Intrinsic Negative) diode (D1) having one of its cathode (CA) and anode (AN) connected to the circuit path (W1). A third terminal (T3) for coupling to a second signal generator (SG2) is connected to the other of the cathode (CA) and anode (AN). The PIN diode (D1) is arranged so that the length of its connection with the circuit path (W1) is electrically short with respect to the signal frequency of the test signal.

Abstract: A clock detector is provided. The clock detector generally comprises a filter, a first branch, a second branch, a latch, and logic. The filter is adapted to receive a clock signal and is coupled to a low threshold inverter in the first branch and a high threshold inverter in the second branch. The latch is adapted to receive the clock signal and is coupled to the first branch, while the logic is coupled to the node between the first branch and the latch, an output of the latch, and the second branch so that it can output a clock detection signal.

Abstract: An output stage for an amplifier is provided. The amplifier generally provides for compensation of an error current generated by the base-collector (or gate-drain) capacitance of a common base (or gate) amplifier transistor. The stage accomplishes this by utilizing a three transistor Wilson current mirror to combine the error current with a mirrored bias current to reduce the load current on the common base (or gate) amplifier transistor.

Abstract: Devices, systems, and methods for providing an on-chip, temperature-stable resistance network for generating a precision current or precision resistance are disclosed. The resistance network includes a first resistance material having a linear, negative temperature coefficient of resistance and a second resistance material having a linear, positive temperature resistance. The first and second resistance materials are arrayed in segments proximate to a local, pulsed thermal gradient and are combined or mixed, i.e., trimmed, to provide a zero or near zero thermal coefficient.

Abstract: Various apparatuses, methods and systems for protecting a driver from electrostatic discharge are disclosed herein. For example, some exemplary embodiments provide a driver, including a buffer, a leakage path blocking transistor connected to an output of the buffer, and an output driver connected to an output of the leakage path blocking transistor. Current from the output driver to the buffer is substantially blocked by the leakage path blocking transistor.

Abstract: A programmable parameter or feature is provided for a power converter through a multi-function connection on the converter controller. The parameter or feature selection is active for programming during a startup mode, and the connection is used for other control purposes during a steady state run mode. A reference signal is read on the multifunction connection during startup mode and a selection of a parameter value or feature is made based on a value of the reference signal. The reference signal is compared to preset, internal reference values to select a desired parameter value or feature. An internal preset value is chosen based on the selection and the programming circuitry is disconnected from the connection to permit alternate functionality for the connection. The programmable circuit permits selection from a variety of parameter values or features based on an external signal, without dedicating an external pin on the controller.

Abstract: A high efficiency precision amplifier which comprises a linear amplifier stage, a class D amplifier stage and a set of switches is provided. Both amplifier stages receive the same input signal. The load is driven by the output of the linear amplifier stage. The set of switches connect the output of the class D amplifier stage to either of the positive and negative supply terminals of the linear amplifier stage and the other of the positive and negative supply terminals of the linear amplifier stage to a negative or positive supply, depending on the polarity of the signal being amplified.

Abstract: In the many microelectronics applications, delays present in circuitry can affect both the design and the function of the circuitry. One example of delays impacting the function of a circuit is a relaxation oscillator, where delays present in comparator circuits and latches can cause its frequency to vary beyond desired ranges. Here, a relaxation circuit with delay compensation is described.

Abstract: Methods and apparatus to pre-compensate for in-phase/quadrature (I/Q) distortion in quadrature transmitters are disclosed. A disclosed example method comprises coupling a portion of an analog baseband in-phase signal to an analog baseband quadrature signal through an impedance, and selecting a resistance value for the impedance to pre-distort the analog baseband quadrature signal to compensate for an error introduced by modulation of the analog baseband in-phase signal and the analog baseband quadrature signal.

Abstract: An electronic device comprising circuitry for providing a Power-on-Reset (POR) signal as a function of a supply voltage level of the circuitry. The circuitry comprises a Vbe-cell or a Vgs-cell comprising a first current path including a first transistor and a second current path including a second transistor. Each transistor has a control terminal for controlling a first current in the first current path and a second current in the second current path, wherein a control voltage level is commonly applied to the control terminals of the first and the second transistor. The control voltage level is derived from the current supply voltage level of the circuitry, and the circuitry further comprises a POR output node for providing a POR output signal, which changes from a first state to a second state in response to the ratio of the magnitudes of the first current and the second current.

Abstract: A process of fabricating an IC is disclosed in which a polysilicon resistor and a gate region of an MOS transistor are implanted concurrently. The concurrent implantation may be used to reduce steps in the fabrication sequence of the IC. The concurrent implantation may also be used to provide another species of transistor in the IC with enhanced performance. Narrow PMOS transistor gates may be implanted concurrently with p-type polysilicon resistors to increase on-state drive current. PMOS transistor gates over thick gate dielectrics may be implanted concurrently with p-type polysilicon resistors to reduce gate depletion. NMOS transistor gates may be implanted concurrently with n-type polysilicon resistors to reduce gate depletion, and may be implanted concurrently with p-type polysilicon resistors to provide high threshold NMOS transistors in the IC.

Abstract: Power amplifiers with reduced idle currents are described. In some examples, a power amplifier includes a driver configured to generate a control signal based on an input signal. The power amplifier also includes a first output transistor configured to selectively provide an output signal via an output channel that has a resistance based on the control signal, and a channel adjuster configured to generate several digital signals based on the control signal. A composite switch, which includes several segment transistors, is included to selectively increase or decrease the output channel resistance based on the digital signals.

Abstract: A voltage-to-current converter is provided. The voltage-to-current converter comprises an amplifier, a resistor network, an R-2R network, and switches. The amplifier has a first input node (which is an input signal), a second input node, and an output node. The resistor network is coupled to the output node of the amplifier, includes a plurality of resistors coupled in series with on another, and includes a plurality of first tap nodes. The R-2R network is coupled to the resistor network and includes a plurality of second tap nodes. Additionally, at least one switch is coupled between the second input node of the amplifier and each first tap node, and at least one switch is coupled between the second input node of the amplifier and each of the second tap nodes.

Abstract: A real time clock (RTC) voltage regulator, a method of regulating an RTC voltage and a power management integrated circuit (PMIC). In one embodiment, an RTC voltage regulator includes a current source configured to provide a first current and a voltage regulator having a common gate amplifier and a power device. The first current is employed to establish a reference voltage for the common gate amplifier and the common gate amplifier is configured to control the power device. The power device is configured to provide an RTC voltage for the common gate amplifier.

Abstract: A method for fabricating a CMOS integrated circuit (IC) and ICs therefrom includes the steps of providing a substrate having a semiconductor surface, wherein the semiconductor surface has PMOS regions for PMOS devices and NMOS regions for NMOS devices. A gate dielectric layer is formed on the PMOS regions and NMOS regions. An original gate electrode layer is formed on the gate dielectric layer. A gate masking layer is applied on the gate electrode layer. Etching is used to pattern the original gate electrode layer to simultaneously form original gate electrodes for the PMOS devices and NMOS devices. Source and drain regions are formed for the PMOS devices and NMOS devices. The original gate electrodes are removed for at least one of the PMOS devices and NMOS devices to form trenches using an etch process, such as a hydroxide-based solution, wherein at least a portion and generally substantially all of the gate dielectric layer is preserved.

Abstract: A comparator component having a comparison circuit and bias generator circuit, with the bias generator circuit also having a same number of transistors connected in an identical configuration, as those contained in the comparison circuit to generate a comparison result based on the bias signal generated by the bias generator circuit. A transistor of the comparison circuit receiving the bias signal is connected to a corresponding transistor in the bias generator circuit, in a current mirror configuration. The same bias circuit may be shared by many comparison circuits of corresponding comparator components. The features can be extended to provide hysteresis.