Abstract: An apparatus is provided. The apparatus comprises a first bipolar junction transistor (BJT) differential pair having a first BJT and a second BJT, a second BJT differential pair having a third BJT and a fourth BJT, a first clamp having a fifth BJT and a sixth BJT, and a second clamp having a seventh BJT and an eighth BJT. The collector and base of the third BJT are respectively coupled to the collector and base of the first BJT, and the collector and base of the fourth BJT are respectively coupled to the collector and base of the second BJT. The bases of first, second, third, and fourth BJTs receive an input clock signal. The emitters of the fifth and sixth BJTs are coupled to the collectors of the first and third BJTs, while the emitters of the seventh and eight BJTs are coupled to the collectors of the second and fourth BJTs. The bases of the fifth and seventh BJT are adapted to receive a low clamping voltage, and the bases of the sixth and eighth BJTs are adapted to receive a high clamping voltage.

Abstract: Memory compiler engineers often focus on the efficient implementation of the largest possible memory configurations for each memory type. The overhead of test and control circuitry within memory implementations is usually amortized across a large number of storage bits. Unfortunately, test structures generally do not scale down with decreasing memory sizes, creating a large area penalty for a design with numerous small memories. One solution is a scannable register file (SRF) architecture using scannable latch bit-cells laid out using a standard cell layout/power template. All sub-cells can be placed in standard cell rows and utilize standard cell power straps. Non-SRF standard cells can be abutted on all sides, placement keep-out regions are not needed. Metal utilization is usually limited to first three metallization layers. The bit-cell is much larger than standard compiled memory bit cells, but has no overhead beyond address decode, word-line drivers, and read-write data latches.

Abstract: An apparatus for effecting sound stage expansion in an audio system presenting two sound channels includes: (a) A first signal source coupled for providing at least one first signal representing a first sound channel to at least one first input locus of a first amplifying unit. The first amplifying unit participates in presenting the first sound channel. (b) A second signal source coupled for providing at least one second signal representing a second sound channel to at least one second input locus of a second amplifying unit. The second amplifying unit participates in presenting the second sound channel. (c) At least one first filter unit coupling the first signal source with at least one of the at least one second input locus. (d) At least one second filter unit coupling the second signal source with at least one of the at least one first input locus.

Abstract: A liquid lens driver 10 has DC-DC converter 12, oscillator 14, pulse width modulator 16, and control logic circuit 18. The output buffer circuit 30 divides converter output voltage Vs of a prescribed amplitude (voltage level), input as the power source voltage, into bipolar, that is, positive/negative, output voltages Out-A, Out-B for output, and, corresponding to the H/L level of PWM signal CPWM, it turns ON/OFF the two output voltages Out-A, Out-B. In this way, from liquid lens driver 10, pulse width modulation (PWM) output voltages Out-A, Out-B are applied as driving voltage VL on electrodes 104, 108 of liquid lens 100.

Abstract: A time-interleaved analog-to-digital converter (ADC) is provided. The ADC generally comprises a first ADC, a second ADC, correction circuit, a divider, and a clocking circuit. The first ADC receives an analog input signal and generates a first output and a differentiated output. The second ADC receives the analog input signal and generates a second output. The correction circuit receives the first output, the second output, and the differentiated output and generates a first error signal and a second error signal. The divider receives the first error signal and the second error signal and generates a timing error by dividing the second error signal by the first error signal, and the clocking circuit receives a clock signal and the timing error and generates a plurality of corrected clocking signals, where each of the first and second ADCs receives at least one of the clocking signals.

Abstract: Methods and apparatus to reduce voltage bounces and spike voltages in switching amplifiers are disclosed. An example method of removing a substrate current from a substrate disclosed herein comprises injecting the substrate current via turning on an active device, forming a low impedance path to ground via a substrate clamp based on the substrate current, and removing the substrate current from the substrate via the substrate clamp.

Abstract: A driver is provided. The driver generally comprises a current source, a current mirror, an amplifier and a presetting circuit. The current source is generally adapted to provide a reference current to the current mirror. The transistor is coupled to the current mirror. The amplifier has the first input that is coupled to the current mirror, a second input that is coupled to a node between the transistor and the current mirror, and an output that is coupled to the control electrode of the transistor. The presetting circuit is coupled to the control electrode of the transistor so that it can preset the potential of the control electrode of the transistor to a potential that allows current driving of the transistor with a predetermined timing after a control signal is received.

Abstract: Increasing the input common-mode range of a circuit which accepts differential signals as inputs. Such an increase may be attained by correcting an input signal at continuous levels or at 2 or more discrete levels) without changing the strength represented by the input signal. In an embodiment, the common-mode component of an input signal is measured, and a correction voltage proportional to the difference between the measured common-mode component and a reference voltage, is generated. The correction voltage is coupled to the input terminals of the differential circuit to correct for any deviations from a desired level of common-mode voltage at the input terminals of the differential circuit. The approaches are applied to a switched-capacitor differential amplifier used in a sample-and-hold portion of an ADC.

Abstract: An error model can be utilized to mitigate errors associated with a conversion system, such as an analog-to-digital or digital-to analog converter. The error model is adaptively calibrated to approximate error characteristics associated with at least a portion of the conversion system, such as a digital-to analog converter. The error model can be generated on-line during system operation or off-line to improve performance of various types of signal converters and systems using such signal converters.

Abstract: An electronic device includes a low drop-out regulator for providing a regulated output voltage. The low drop-out regulator generally comprises a power MOSFET transistor having a gate coupled to a driver. The driver has a first path including an NMOS transistor and being coupled to the gate of the power MOSFET, a second path having a PMOS transistor and being coupled to the gate of the power MOSFET, and a switch for alternately switching between the first and second paths so as to provide a voltage to the gate of the power MOSFET ranging from ground to a power supply level.

Abstract: For differential signal transmission (especially in high speed applications), intra-pair skew between paths carrying complementary portions of a differential signal can significantly affect performance. Conventional de-skew circuits employ simple filters (i.e., low-pass filters) to operate as delay elements to account for skew; however, these filters can distort the differential signal, which can also adverse affect performance. Here, an all-pass, adjustable delay element and de-skew circuit are provided to allow for compensation of skew without degrading the differential signal as conventional circuit do and, thus, having better performance characteristics.

Abstract: A self-calibrating, adaptive equalization system for generating an ideal digital signal is disclosed. The adaptive equalization system includes an equalizer and a high-gain buffer. The equalizer includes a first equalizer loop that feeds-back a control voltage to the equalizer and the high-gain buffer that includes a second equalizer loop that feeds-back a high-pass-to-low-pass filter ratio signal. Each of the first and second equalizer loops has a high-pass and a low-pass filter, rectifying circuits for each of the filters, and an integrating circuit that compares signal energy output from the rectifiers. The adaptive equalization system generates an ideal digital signal.

Abstract: A method and system for providing automatic gain control for a differential amplifier are provided. An impedance network is set to have a first impedance that corresponds to a first gain for a differential amplifier, which amplifies an input signal by the first gain. Once the amplified input signal is greater than a first threshold voltage, the impedance network is set to have a second impedance that corresponds to a second gain for the differential amplifier, which amplifies the input signal. Once amplified input signal is greater than a second threshold voltage and a predetermined period has lapsed, the impedance network is reset to have the first impedance that corresponds to a first gain for the differential amplifier.

Abstract: An apparatus having an input voltage and an output voltage is provided. The apparatus comprises a switch that receives the input voltage and that is adapted to be coupled to a load, a modulator having a timing signal, a compensator that is coupled to the modulator and that includes an amplifier, an overcurrent circuit, and a sampler. The modulator is coupled to the switch and the modulator actuates the switch at a first frequency. The amplifier amplifies the difference between at least a portion of the output voltage with a predetermined reference voltage and outputs an amplified voltage. The overcurrent circuit receives the amplified voltage and outputs an overcurrent signal to the modulator.

Abstract: One embodiment of an apparatus for testing an amplifier includes an amplifier having a driver and a filter, the filter being connected between an output of the driver and an output of the amplifier. The filter is operable to produce a demodulated output signal from a higher frequency modulated signal at the driver output. The apparatus also includes a voltage level detector connected to the driver output and a control circuit operable to detect at least one fault based on a voltage level measured at the driver output by the voltage level detector.

Abstract: Chopper stabilized operational amplifiers are in common use. One drawback of these amplifiers, however, is that there is an inherent tone present at the chopper frequency. Conventional circuits have attempted to reduce the effects of this tone by using various filtering schemes, such as a notch filter. Here, however, a track-and-hold circuit is used in conjunction with matched amplifiers to compensate for this tone.

Abstract: An apparatus is provided. The apparatus comprises a current sensor, an error amplifier, a comparator, an analog-to-digital converter (ADC), control logic, and drivers. The error amplifier is adapted to receive a reference voltage and a feedback voltage, and the comparator has a first input terminal and a second input terminal, where the sum of at least a first portion of a common mode voltage and an output of the error amplifier is input into the first input terminal, and wherein the sum of at least a second portion of the common mode voltage and an output of the current sensor is input into the second input terminal. The ADC receives the sum of the second portion of the common mode voltage and the output of the current senor. Additionally, the ADC has a plurality of internal threshold voltages that are between the common mode voltage and an overcurrent limit adjustment voltage.

Abstract: An electronic device supplied by multiple supply voltages includes a bias current generating stage and maximum current selection stage. The bias current generating stage comprises a crude bias current generator for generating an crude bias current during a power up phase in which at least one of the multiple supply voltages has not yet reached its target supply voltage level, a reference current stage for providing a reference current having a target current value greater than the target value of the crude bias current when the multiple supply voltages have reached their target supply voltage levels. The maximum current selection stage is adapted to continuously output a bias current which is the maximum current of the crude bias current and the reference current.

Abstract: Systems and methods for reduced distortion in a class D amplifier are provided. An “ideal” digital output signal is produced. The “ideal” digital output signal is then compared to the actual output signal in an error amplifier. The integrator input is the difference between the output stage waveform and the ideal output stage waveform. The net input to the integrator now comprises the imperfections of the power stage, and the feedback loop drives their average to zero. This error is then amplified and integrated. The integrated signal is than applied to a summer where it is added to the analog input. Then as in the typical Class D amplifier, the integrated signal is compared in an error amplifier to a ramp signal generated from the ramp generator.

Abstract: A sensor having photodiodes whose sensitivity and storage capacity can be increased is provided. The sensor is formed by arranging the photodiodes in an array with first region of second conductivity type is formed on the principal surface of a substrate of a first conductivity type. A pixel separating region of the first conductivity type is formed to penetrate through the first semiconductor region to separate the regions of the adjacent photodiodes. A second region of the second conductivity type used to drain excess charge is formed in substrate at a position away from the junction surface between substrate and the first region and below the junction surface.