Abstract: In many applications, “dying gasp” periods following power down are used. Conventional circuits supply energy for the “dying gasp” periods generally by use of large external capacitors that are bulky and expensive. Here, a dying gasp charge controller is employed that allows for the use of smaller capacitors at higher voltages, which maintains or exceeds the energy storage capacities of conventional circuits.

Abstract: An electronic device is provided comprising a driver for light emitting semiconductor devices. The driver includes a first MOS transistor (MN1) coupled with a channel to the light emitting semiconductor device at an output node. The first MOS transistor (MN1) is configured to determine a current through the light emitting semiconductor device (LED). A control loop is provided so as to control the first MOS transistor to maintain the magnitude of the current through the light emitting semiconductor device at a target value when a voltage drop across the first MOS transistor (MN1) changes. A second MOS transistor is coupled to the output node and biased so as to supply an auxiliary current to the output node, when the voltage drop across the first MOS transistor drops below a minimum voltage level and a feedback loop is provided to reduce the current through the light emitting semiconductor device by an amount proportional to the auxiliary current.

Abstract: The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively apply strain to multiple regions of a semiconductor device. A semiconductor device having one or more regions is provided (102). A strain inducing liner is formed over the semiconductor device (104). A selection mechanism, such as a layer of photoresist or UV reflective coating is applied to the semiconductor device to select a region (106). The selected region is treated with a stress altering treatment that alters a type and/or magnitude of stress produced by the selected region (108).

Abstract: Load switches are relatively common and in use with a variety of applications, and conventional load switches have been designed to have continually operating protection circuitry, which can consume a great deal of power. Here, a load switch integrated circuit (IC) is provided where a controller within the IC activates and deactivates various protection circuits in a sequence, allowing the protection circuit to protect the IC while also reducing power consumption.

Abstract: A method of manufacturing a single-electron transistor device is provided. The method includes forming a thinned region in a silicon substrate, the thinned region offset by a non-selected region. The method also includes forming at least one quantum island from the thinned region by subjecting the thinned region to an annealing process. The non-selected region is aligned with the quantum island and tunnel junctions are formed between the quantum island and the non-selected region. The present invention also includes a single-electron device, and a method of manufacturing an integrated circuit that includes a single-electron device.

Abstract: Various driver circuit apparatuses and methods for driving an electrical signal are disclosed herein. For example, some embodiments provide a driver circuit including a controlled-slew rate input circuit, a buffer that is connected to the controlled-slew rate input circuit, and an output driver that is connected to the buffer. The driver circuit is adapted to drive an output signal from the output driver based on an input signal to the controlled-slew rate input circuit. The impedance at the input of the output driver is lower than the impedance at the output of the controlled-slew rate input circuit.

Abstract: A D-class amplifier that can suppress noise generated when a D-class amplification operation is started/stopped. When a D-class amplification operation is started/stopped, the pulse widths and pulse interval of output signals Pout1, Pout2 are gradually changed, so it is possible to prevent a large variation in the signal fed as a differential signal of output signals Pout1, Pout2 to the load, and it is possible to reduce noise. That is, by gradually changing the pulse interval while keeping the pulse widths of output signals Pout1, Pout2 constant, it is possible to suppress variation in the relatively high frequency component corresponding to the component of the pulse signal. Also, by gradually changing the widths of output signals Pout1, Pout2 while keeping the pulse interval constant, it is possible to suppress variation in the relatively low frequency component corresponding to the average value of the pulse signal.

Abstract: A voltage supply circuit and a circuit device can reduce the noise in the output of the circuit when the power to the circuit is turned on and off and can shorten the time required to start or stop the operation of the circuit. When the supply of power to signal processing part 10 is started or stopped, reference voltage Vref supplied to signal processing part 10 is varied continuously to reduce the high-frequency noise in the output of signal processing part 10. Also, when the setpoint value of the waveform of reference voltage Vref is generated by digital signal processing in voltage setting part 30, the desired waveform can be generated without being limited by the values of the circuit elements or the circuit configuration. The output noise of signal processing part 10 can be reduced, and the time that reference time Vref varies can be shortened.

Abstract: A digital circuit may have at least two asynchronous clock domains with a controller responsive to a first domain clock signal and a target responsive to a second domain clock signal. A first domain control signal pulse is generated in response to the first domain clock signal for controlling the target. Each assertion the first domain control signal pulse is detected and used to form a second domain control signal pulse synchronized to the second domain clock signal. The target is controlled using the second domain control signal pulse. If the target is a clear-on-read register, contents of the clear-on-read register are latched in a feedback register in response to the first domain control signal pulse and provided to the controller. Each bit of the clear-on-read register is reset in response to the second domain control signal pulse only if the corresponding latched content of each bit in the feedback register is a logical one.

Abstract: Traditionally, time stamp circuits have been used for precise digital time measurements. The resolution of these types of circuits, though, was generally limited by clock speed. Here, an apparatus is provided that performs time stamp operations and is not generally limited by clock speed. This apparatus generally uses an interpolator, counter, lathing circuits, and a synchronizer. Typically, the interpolator provides a residue signal to the synchronizer, and the synchronizer can determines whether to add the interpolation signal to a counter state based at least in part on a comparison of an event signal and the residue signal.

Abstract: A circuit for independently controlling slew and propagation delay of a current DAC is provided. The circuit applies dual slope technique with feed-back control the gate (or control electrode) of a switching transistor to make propagation delay independent control from rise/fall slew rate. This allows one to adjust propagation delay and current slew rate separately to achieve better performance.

Abstract: A method for determining whether a tire is in rotation is provided. A measured acceleration is compared to a first threshold after a first timer indicates that a first period has lapsed, and indication that the tire is in rotation is provided if at least one of the measured accelerations is greater than the first threshold. If an absolute difference between consecutive measured accelerations is greater than a second threshold, an indication that the tire is in rotation is also provided. Additionally, the second timer is started if the absolute difference is greater than the second threshold and if a second timer is not running, and indication that the tire is rotating is provided if the absolute difference is less than a predetermined threshold and if the second timer is running.

Abstract: A semiconductor device that attenuates light to the circuit element area is provided. The semiconductor device includes light-sensitive element area formed on substrate and a circuit element area formed on the substrate. Additionally, a multilayer wiring area is formed on circuit element area. A Tantalum film (which is generally made of tantalum or a tantalum compound) is formed on the surface of the multilayer wiring area to attenuate incident light on circuit element area.

Abstract: Apparatus and method to scramble data prior to placing it on a bus or in memory uses embedded hardware keys for encryption/decryption. The hardware keys may be used in addition to software encryption. Different hardware keys may be used to process most significant bits and least significant bits of a data word. Different hardware keys may be used to process messages from/to different channels. The hardware key may be comprise a series of fixed logic cells.

Abstract: In a traditional, fully-isolated bandgap reference circuits, it was difficult to detect currents that are proportional to absolute temperature (PTAT). Here, a PTAT reference in a fully isolated NPN-based bandgap references are disclosed. These circuits in particular are able to make detections using various current without the need for stand-along operational amplifiers.

Abstract: A touch screen digitizing system includes a first resistive screen and a touch screen controller including an ADC and self-test circuitry having a driver switch coupled between a reference voltage and a first terminal of the first resistive screen, and a first test switch coupled between ground and a conductor connected to generate a first test voltage on the conductor indicative of connection resistance between the first resistive screen and the touch screen controller. Another test switch couples the test voltage to an input of the ADC. An output of the ADC is compared with a reference to determine whether the connection resistance is excessive. Connection resistance between a second resistive screen and the touch screen controller is measured similarly. Similar self-test circuitry operates to detect a short circuit between the first resistive screen and the second resistive screen.

Abstract: A current reference circuit is disclosed. A small startup current is defined as the base current into a bipolar transistor with its collector-emitter path connected in series with a resistor between the power supply voltage and ground. This startup current is conducted via a diode-connected MOS transistor in a first leg of a current mirror. Temperature compensation is maintained by a reference leg in the current mirror that includes a bipolar transistor having an emitter area N times larger than that of a bipolar transistor in a second leg of the current mirror, to establish a temperature-compensated current in the reference leg. A compensation capacitor connected between the collector and base of a bipolar transistor in the first leg suppresses oscillation, and can be modest in size due to the Miller effect.

Abstract: With high speed, high resolution time-interleaved (TI) analog-to-digital converters (ADCs), bandwidth mismatches between the various ADC branches can pose a significant problem. Previously, though, no adequate solution has been found. Here, a method and apparatus are provided that can calculate and compensate for bandwidth mismatches in a TI ADC, enabling a high speed, high resolution TI ADC to be produced.

Abstract: Previously, when designing receivers for radio frequency (RF) or wireless communications, designers chose between time-interleaved (TI) analog-to-digital converters (ADCs) for intermediate frequency architectures and dual channel ADCs for direct conversion architectures. Here, similarities between TI ADCs and dual channel ADC were recognized, and an ADC that has the capability of operating as a TI ADCs and dual channel ADC is provided. This allows designer to have greatly increased flexibility during the design process which can greatly reduce design costs, while also allowing the manufacturer of the ADC to realize a reduction in its operating costs.

Abstract: A gated resonant tunneling diode (GRTD) that operates without cryogenic cooling is provided. This GRTD employs conventional CMOS process technology, preferably at the 65 nm node and smaller, which is different from other conventional quantum transistors that require other, completely different process technologies and operating conditions. To accomplish this, the GRTD uses a body of a first conduction type with a first electrode region and a second electrode region (each of a second conduction type) formed in the body. A channel is located between the first and second electrode regions in the body. A barrier region of the first conduction type is formed in the channel (with the doping level of the barrier region being greater than the doping level of the body), and a quantum well region of the second conduction type formed in the channel. Additionally, the barrier region is located between each of the first and second electrode regions and the quantum well region.