Abstract: A multi-chambered system for electroplating metal layers on a semiconductor substrate. The system comprises a fluid reservoir having at least a first chamber and a second chamber. A cathode is located in the first chamber, an anode is located in the second chamber, and a shield is located between the cathode and anode. The cathode is configured to be electrically coupled to a semiconductor substrate locatable in the first chamber. The anode is configured to oppose a first major surface of the semiconductor substrate. The shield is configured to deter electrolytic fluid communication between the first and second chamber, other than through predefined openings in the shield.

Abstract: An apparatus is provided that uses a first level shifter for performing a voltage shift of a low level input signal of a first voltage domain to a high level output signal of a second voltage domain. The first level shifter comprises a storing element in the second voltage domain, an input stage coupled to the storing element for providing a signal state to be stored in the storing element and a feedback loop from an output of the storing element to the input stage for controlling the input stage in response to a transition of a high level output signal of the storing element.

Abstract: A method of generating a scalable OPC model for composing reticle pattern files from IC layouts using 2D test patterns is disclosed. The 2D test patterns include basic features which replicate features found in advanced ICs. Variations of feature dimensions and structure pitches provide measurement data which enables the scalability of the OPC model. A method of checking reticle pattern files for features which cannot be modeled by the scalable OPC model is also disclosed.

Abstract: One-sided pulse width modulated (PWM) amplifiers are disclosed.

Abstract: Traditionally, switching amplifiers (i.e., class-D and class-G) with negative supply rails had issues with direct current (DC) power loss, included large external capacitors, had a comparative reduction in efficiency, and oftentimes included separate power management circuits. Here, a class-D amplifier is provided with an output stage that provides negative supply voltages, positive supply voltages, and ground. Essentially, this amplifier provides some of the benefits of the conventional amplifiers without the drawbacks.

Abstract: Because of variations in open loop gain and bandwidth in successive approximate register (SAR) analog-to-digital converters (ADCs), designing amplifiers with the desired characteristics is difficult. Here, a multipath amplifier is provided that accounts for the variations in open loop gain and bandwidth. Preferably, a number of cascaded amplifiers are provided that can auto-zero to account for offset voltages so as to allow the multipath amplifier to be stable over the desired open loop gains and bandwidths.

Abstract: In a method and apparatus for saving power in a device coupled to a bus, the device is placed to operate in a power saving mode by powering off a selective portion of the device including a device clock. If data communication over the bus is addressed to the device then the selective portion of the device, including the device clock, is triggered to return to a power on state from the power off state. The data communication is stored in shadow registers using a bus clock while the device clock is transitioning to the power on state. The data communication stored in the shadow registers is transferred to a register map under the control of the device clock operating in the power on state. Upon completion of the transfer of the data communication to the register map, the device is returned to operate in the power saving mode.

Abstract: A minimal area, power efficient, high swing and monolithic ground centered headphone amplifier circuit operable on a low voltage. An input amplifier stage includes a first input terminal and a second input terminal and having a first gain. An output amplifier stage is coupled to an output of the input amplifier stage to provide an output signal and having a second gain. A feedback network coupled between the first input terminal and the output of the output amplifier stage. A level shifting unit coupled to the first input terminal and the feedback network. A charge pump coupled to the output amplifier stage to generate a negative supply voltage and to minimize a noise associated with the negative supply voltage using a loop gain of the amplifier, wherein the loop gain is a combination of the first gain, the second gain, and a gain of the feedback network.

Abstract: A relatively low frequency chopping operation is applied to a delta-sigma ADC to reduce DC offsets resulting from non-ideal component operation. Sequential chopping takes place outside a closed loop and may include an inverted polarity feedback for a part of the chopping period. Nested chopping involves chopping within the closed loop, and may include an inverted polarity feedback and a time shift. The feedback compensation for sequential and nested chopping permits the correct polarity feedback to be provided at the desired time in conjunction with sampling and quantization events. Integrating capacitor(s) may be swapped in relative polarity during nested chopping to preserve residual conversion information for the desired polarity. The ADC operation is non-temperature dependent and avoids modification to the useful signal, resulting in higher accuracy.

Abstract: A converter has a single inductor with a first terminal connectable to a first terminal of the supply input through a first power transistor and a second terminal connectable to a second terminal of the supply input through a second power transistor. A first rectifier element connects the first terminal of the inductor with a first output terminal, and a second rectifier element connects the second terminal of the inductor with a second output terminal. A resistive voltage divider is connected between the first and second output terminals. A control circuit uses an input from the voltage divider as a reference input voltage and provides an output current to the second terminal of the supply input in response to any voltage difference between the reference input voltage and the second terminal of the supply input. This provides a virtual common reference potential at the second terminal of the supply input, which is thus a common ground (GND) terminal.

Abstract: An apparatus that is adapted to receive signals from an Inter-Integrated Circuit (I2C) bus is provided. The apparatus comprises a serial data (SDA) filter, a serial clock (SCL) filter, I2C interface logic, and operational circuitry. The SDA filter is adapted to receive an SDA signal from the I2C bus and includes a hold terminal and a disable terminal. The hold terminal of the SDA filter issues a disable signal when a transient in the SDA signal is detected. The SCL filter is adapted to receive an SCL signal from the I2C bus and includes a hold terminal and a disable terminal. The hold terminal of the SCL filter issues a disable signal when a transient in the SCL signal is detected. Additionally, the hold terminal of the SCL filter is coupled to the disable terminal of the SDA filter, and the hold terminal of the SDA filter is coupled to the disable terminal of the SCL filter.

Abstract: A touch screen system includes a touch screen assembly (30,31) and a touch screen controller (1A) coupled to terminals (24,25,26,27) of the touch screen assembly (30,31), the touch screen controller (1A) including a controller (41) and an analog to digital converter (22) for generating multiple digital data numbers representing multiple coordinate values, respectively, of a particular touch point (Q) of the touch screen assembly (30,31) in response to control signals (42) generated by the controller (41). A sorting technique is performed to sort the digital data numbers in order of their values, respectively. An averaging technique is performed on at least some of the sorted digital data numbers, including a median sorted digital number.

Abstract: Methods and apparatus to provide clock resynchronization in communication networks are disclosed. An example method of clock resynchronization disclosed herein comprises determining a vote based on adjacent samples occurring within a single bit interval in a sampled data stream, wherein the vote comprises an early vote when the adjacent samples indicate a sampling phase of a sampling clock is early relative to a center position in the bit interval and wherein the vote comprises a late vote when adjacent samples indicate the sampling phase is late relative to the center position, tracking a running difference between a number of early votes and a number of late votes in a plurality of votes corresponding to a plurality of adjacent samples, and adjusting the sampling phase when the running difference reaches a threshold.

Abstract: A digital video system (2) is disclosed, in which an analog input video signal is sampled at an optimum sample phase (Pnc), and converted to a digital datastream for display. A phase-locked loop (12) generates a plurality of sample clock phases. One of the sample clock phases (Pnc) is applied to an analog-to-digital converter (10), which digitizes the analog input video signal accordingly. Phase alignment circuitry (20) is provided that includes three sample-and-hold circuits (22b, 22c, 22a) that sample the analog input video signal, in parallel with the analog-to-digital converter (10), at times before, at, and after the current sample clock phase used by the analog-to-digital converter (10). The earlier and later sampled voltages are compared against the current sampled voltages to generate difference voltages that are each compared against a threshold voltage (Vthr).

Abstract: An apparatus is provided. The apparatus comprises a first bipolar junction transistor (BJT) differential pair having a first BJT and a second BJT, a second BJT differential pair having a third BJT and a fourth BJT, a first clamp having a fifth BJT and a sixth BJT, and a second clamp having a seventh BJT and an eighth BJT. The collector and base of the third BJT are respectively coupled to the collector and base of the first BJT, and the collector and base of the fourth BJT are respectively coupled to the collector and base of the second BJT. The bases of first, second, third, and fourth BJTs receive an input clock signal. The emitters of the fifth and sixth BJTs are coupled to the collectors of the first and third BJTs, while the emitters of the seventh and eight BJTs are coupled to the collectors of the second and fourth BJTs. The bases of the fifth and seventh BJT are adapted to receive a low clamping voltage, and the bases of the sixth and eighth BJTs are adapted to receive a high clamping voltage.

Abstract: A method for driving a light-emitting semiconductor is provided. A supply voltage is converted into a secondary output voltage for supplying the light-emitting semiconductor with an output voltage. A level for the supply voltage at the beginning of a high current phase of the light-emitting semiconductor is sensed. A threshold voltage level for the supply voltage level is determined based on the sensed level. The high current phase with the light-emitting semiconductor is stated. The sensed level is continuously compared with the threshold voltage level, and an output current through the light-emitting semiconductor is controlled such that the sensed level does not drop below the threshold voltage level.

Abstract: With conventional redrivers used for external Serial Advanced Technology Attachment (eSATA), there is no ability to indicated to a host that an external device (like a hard disk drive) is not present. As a result, power is consumed by a host because of nearly continual transmission of communication reset signals. Here, a redriver has been provided that includes a cable disconnect terminal and circuitry within a controller that is able to detect whether an external device is present. This redriver enables a host to be powered down or placed in a low power mode while also enabling the use an eSATA compliant connector.

Abstract: A capacitance measurement system precharges first terminals (21-0 . . . 21-k . . . 21-n) of a plurality of capacitors (25-0 . . . 25-k . . . 25), respectively, of a CDAC (capacitor digital-to-analog converter) (23) included in a SAR (successive approximation register) converter (17) to a first voltage (VDD) and pre-charges a first terminal (3-j) of a capacitor (CSENj) to a second voltage (GND). The first terminals are coupled to the first terminal of the capacitor to redistribute charges therebetween so as to generate a first voltage on the first terminals and the first terminal of the capacitor, the first voltage being representative of a capacitance of the first capacitor (CSENj). A SAR converter converts the first voltage to a digital representation (DATA) of the capacitor. The capacitance can be a touch screen capacitance.

Abstract: One well known problem associated with voltage controlled oscillators or VCOs is phase noise, and it is desirable to reduce phase noise in order to improve VCO performance. Here, a VCO is provided where gain elements are provided that reduce phase noise. These gain elements are generally comprised of oscillator tanks.

Abstract: The present invention provides a body bias coordinator for use with a transistor employing a body region. In one embodiment, the body bias coordinator includes a control unit configured to control the transistor and make it operable to provide a virtual supply voltage from a source voltage during activation of the transistor. The body bias coordinator also includes a connection unit coupled to the control unit and configured to connect the body region to the virtual supply voltage during activation of the transistor. In an alternative embodiment, the connection unit is further configured to connect the body region to another voltage during non-activation of the transistor. These embodiments improve transistor active and passive performance, permit smaller transistor sizing and reduce leakage current.