Abstract: A low pressure process is described for the anisotropic etching of a titanium or tantalum silicide layer formed over a polysilicon layer on a gate oxide layer, and then masked. The etch process is carried out at a low pressure of about 10 milliTorr to about 30 milliTorr using Cl.sub.2 and HBr etching gases, preferably only Cl.sub.2 at the etching gas, to etch the silicide without undercutting the mask layer. In a preferred embodiment, etch residues are also eliminated by the use of only Cl.sub.2 as the etching gas in the low pressure etch step. In the most prefferred embodiment, any bulges which might otherwise remain in the sidewalls of the underlying polysilicon layer, are also eliminated by using only HBr as the etching gas in the over-etch step, which is highly selective to oxide to protect the underlying gate oxide layer; resulting in an anisotropic etch of both the titanium/tantalum silicide and polysilicon layers, without leaving etch residues on the wafer surface.

Abstract: A low temperature process is described for forming a coating or powder comprising one or more metals or metal compounds by first reacting one or more metal reactants with a halide-containing reactant to form one or more reactive intermediates capable of reacting, disproportionating, or decomposing to form a coating or powder comprising the one or more metal reactants. When one or more metal compounds are formed, either as powders or as coatings, a third reactant may be injected into a second reaction zone in the reactor to contact the one or more reactive intermediates formed in the first reaction zone to thereby form one or more metal compounds such as metal nitrides, carbides, oxides, borides, or mixtures of same.

Abstract: The invention comprises an improvement in the process wherein a polysilicon layer, which is formed over a step on an integrated circuit structure and masked with a photoresist, is anisotropically etched to remove the exposed portions of the polysilicon layer leaving sidewall residues of a polymerized silicon/oxide-containing material adjacent the polysilicon lines. The improvement comprises treating the integrated circuit substrate with an aqueous hydroxide/peroxide solution to remove the residues of polymerized silicon/oxide-containing material, without undercutting the remaining polysilicon.

Abstract: A polysilicon deposition process is disclosed for forming a doped polysilicon layer over a stepped surface on a semiconductor wafer having the deposition characteristics and resulting profile of an undoped polysilicon layer which comprises: depositing doped polysilicon on the stepped surface, depositing undoped polysilicon over the doped polysilicon, repeating the doped and undoped depositions cyclically until the desired amount of polysilicon has been deposited, and then annealing the deposited polysilicon to uniformly distribute the dopant throughout the entire deposited polysilicon layer.

Abstract: An improvement in a method for cleaning a CVD deposition chamber in a semiconductor wafer processing apparatus is described. The improvement comprises the treatment of fluorine residues in the CVD deposition chamber, left from a prior fluorine plasma cleaning step, by contacting such fluorine residues with one or more reducing gases which will react with the fluorine residues to form one or more gaseous or solid reaction products or a mixture of same.

Abstract: A process for efficiently removing halogenated organic compounds from contaminated aqueous liquids is described which comprises contacting the contaminated liquid with a photocatalyst while simultaneously exposing the contaminated liquid to both acoustic energy and light energy to efficiently decompose the halogenated organic compounds.

Abstract: A method and apparatus are described for inhibiting visual obstruction of the window of a semiconductor etch process chamber by deposition of each byproducts thereon by selectively heating the window surfaces adjacent one edge of the window to thereby form a cool region on the window surfaces adjacent the opposite edge of the window whereby the center of the window will remain substantially clear of such depositions. The apparatus for carrying out the method of the invention comprises a first heat transmitting structure disposed on one surface of an optically transparent window adjacent one edge, and a second heat transmitting structure disposed on the opposite surface of the optically transparent window adjacent the same edge to thereby provide even heating of both surfaces of the window adjacent the one edge, thereby creating a cooler zone on the window surfaces adjacent the opposite edge of the window.

Abstract: A process is described for plasma-assisted etching of an aluminum layer to form aluminum lines while fabricating an integrated circuit structure on a semiconductor wafer using one or more bromine-containing etch gases, and optionally SF.sub.6 in combination with the bromine-containing gas or gases, which will not result in the formation of corrosive residues such as normally occurs when chlorine-based etchants are used.

Abstract: A metal lead frame for an integrated circuit package is disclosed having stress relieving means formed therein to inhibit breakage of a thermally mismatched silicon die subsequently attached thereto and then heated during normal operation of the device. The stress relieving means may comprise parallel grooves formed in one or both surfaces of the central portion of the lead frame where a silicon integrated circuit die will subsequently be bonded to the lead frame. Preferably, the grooves are formed in both axes comprising the plane of the lead frame and may be formed on both surfaces of the lead frame. The stress relieving means may also comprise a series of openings cut through the central portion of the lead frame.

Abstract: A process is disclosed for accurately forming an etch mask over the uneven surface of a semiconductor wafer using a multilayer photoresist. The process comprises forming a first or lower photoresist layer on the surface of a semiconductor wafer, forming one or more intermediate layers over the first photoresist layer, forming a second or upper photoresist layer over the one or more intermediate layers on the wafer, photolithographically forming a pattern in the second photoresist layer, reproducing the pattern in the intermediate layer below the second photoresist layer, removing the remainder of the upper photoresist layer, and then reproducing the pattern in the first photoresist layer using the pattern formed in the intermediate layer as a mask. In one embodiment a single intermediate layer is used in which the mask pattern is partially etched prior to removal of the upper photoresist.

Abstract: A planarizing process is disclosed for planarizing an integrated circuit structure using a low melting inorganic planarizing material which comprises flowing while depositing a low melting inorganic planarizing layer such as a boron oxide glass over a layer of insulating material such as an oxide of silicon and then dry etching the low melting inorganic planarizing layer to planarize the structure. The method eliminates the need for separate coating, drying, and curing steps associated with the application of organic-based planarizing layers usually carried out outside of a vacuum apparatus. In a preferred embodiment, the deposition steps and the etching step are carried out without removing the integrated circuit structure from the vacuum apparatus. An additional etching step may be carried out after depositing the insulating layer and prior to deposition of the planarizing layer to remove any voids formed in the insulating layer.

Abstract: Process and apparatus are disclosed for forming a layer of a stoichiometric metal compound on a semiconductor wafer by reactive sputtering a metal target in a chamber in the presence of a reactive gas, wherein the negative potential on a metal target is increased or decreased to change the supply of sputtered metal atoms available to react with the atoms of the reactive gas at a fixed flow of the gas by resetting the power level of a constant power source electrically connected to the target and a path is provided for the flow of reactive gas to the zone between the target and the wafer, while restricting the travel of the stoichiometric metal compound being formed from the zone to thereby provide a stoichiometric ratio of sputtered metal atoms and reactive gas atoms adjacent the wafer to form the stoichiometric metal compound on the wafer.

Abstract: A multistep aluminum sputtering process is disclosed wherein aluminum is sputtered onto the surface of a semiconductor wafer and low areas between closely spaced apart raised portions on the wafer, such as closely spaced apart steps, narrow trenches, or small diameter vias, are completely fulled in by the sputtered aluminum. This results in the formation of an aluminum layer which is not thinned out in such low areas, and which has a surface which ranges from substantially planar to a positive slope, such as shown at 24' and 26' in FIG. 2. The first step is carried out by sputtering from about 200 to about 2000 Angstroms of aluminum while the wafer temperature is within a range of from about 50.degree. C. to about 250.degree. C. and the sputtering plasma is at a power of from about 1 to about 16 kilowatts.

Abstract: Highly doped short channel NMOS devices with punch-through protection; intrinsic NMOS devices with low threshold voltage; and long channel NMOS and PMOS devices with low body factor; are constructed by providing one or more lightly doped P regions in a semiconductor wafer in which intrinsic and long channel NMOS devices may be constructed, and one or more N wells in the wafer where PMOS devices can be constructed; forming isolation oxide on the wafer before implanting the wafer to inhibit field inversion in N channel (NMOS) devices; masking N regions of the wafer except where long channel PMOS devices will be formed and portions of P regions of the wafer where long channel NMOS devices will be constructed, and optionally masking P regions where either intrinsic NMOS devices or short channel NMOS devices will be formed; and then implanting the wafer to simultaneously provide a field implant below the isolation oxide, adjacent regions where NMOS devices will be formed, as well as optionally providing a deep imp

Abstract: An improved plasma etching apparatus is disclosed comprising an etch chamber having inner metal surfaces with a conductive coating formed thereon which is capable of protecting such inner metal surfaces from chemical attack by reactant gases such as halogen-containing gases used in said chamber during plasma etching processes. In a preferred embodiment, at least about 0.2 micrometers of a carbon coating is formed on the inner metal surfaces of the etch chamber by a plasma-assisted CVD process using a gaseous source of carbon and either hydrogen or nitrogen or both.

Abstract: A method and apparatus are disclosed for removing one or more materials deposited on the backside and end edges of a semiconductor wafer which comprises urging the front side of the wafer against a faceplate in a vacuum chamber; flowing one or more gases through a space maintained between the front side of the wafer and the faceplate; and forming a plasma in a gap maintained between the backside of the wafer and susceptor to remove materials deposited on the backside and end edge of the wafer; the gas flowing through the space between the front side of the wafer and the faceplate acting to prevent the plasma from removing materials on the front side of the wafer.

Abstract: A corrosion-resistant protective coating on an aluminum substrate capable of withstanding corrosion attack by process halogen gases and plasmas is disclosed. The protective coating is formed by contacting an aluminum oxide layer on an aluminum substrate with one or more fluorine-containing gases at an elevated temperature. In a preferred embodiment, a high purity corrosion-resistant protective coating on an aluminum substrate capable of withstanding corrosion attack may be formed by first forming a high purity aluminum oxide layer on the aluminum substrate and then contacting the aluminum oxide layer with one or more high purity fluorine-containing gases at an elevated temperature to form the high purity corrosion resistant protective coating theron.

Abstract: A plastic encapsulated integrated circuit package is disclosed which comprises a multilayer ground plane assembly bonded to a lead frame with an integrated circuit die bonded to the composite assembly. The multilayer ground plane assembly is first formed by bonding together a copper sheet and a thermally conductive polyimide material insulating layer to which is also bonded a layer of a b-stage epoxy resin. The ground plane assembly is then bonded to the lead frame by placing the b-stage epoxy layer of the ground plane assembly against the lead frame and heating the ground plane assembly and lead frame to a temperature of from about 120.degree. C. to just under 200.degree. C. for a time period not exceeding about 10 seconds to bond the b-stage epoxy resin to the lead frame without oxidizing it. An integrated circuit die is then attached to the composite assembly with an epoxy adhesive and the die attached assembly is then cured in a non-oxidizing atmosphere in an oven at approximately 150.degree. C.

Abstract: An integrated circuit lead assembly structure is disclosed which comprises one or more pc boards, having a first lead pattern adjacent one surface of a pc board and a second lead pattern adjacent another surface of a pc board with at least a portion of the leads of the first lead pattern running perpendicular to corresponding leads of the second lead pattern to reduce crosstalk and coupling between the leads. An array of bonding pads is provided on one surface of the structure together with a die mounting area and electrical connection is made from the bonding pads to leads not on the same surface through vias or plated-through holes which respectively pass through the structure from the bonding pad to the appropriate lead. When a laminate of several pc boards is used, power and/or ground electrodes may be provided on other surfaces and also electrically connected to one or more bonding pads.

Abstract: A method and apparatus is disclosed for handling semiconductor wafers used for the production of integrated circuit structures which permits moving the wafer from one processing station to another without direct handling of the wafer and which also permits equal processing of both the top and bottom surfaces of the wafer. A wafer retaining ring is disclosed having structure for engaging the retaining ring to transfer the wafer and the retaining ring from one processing station to another to perform a plurality of processing steps on one or both surfaces of the wafer without direct handling of the wafer. The retaining ring is also provided with structure for engaging the end edges of the wafer leaving both the top and bottom surfaces of the wafer equally exposed for processing. The retaining ring has an inner diameter sufficiently large with respect to the outer diameter of the wafer so as to not interfere with processing by shadowing either side of the wafer.