Abstract: A process is disclosed for forming a layer of titanium nitride on a semiconductor wafer which comprises forming a titanium layer on the wafer in a vacuum deposition chamber in the substantial absence of oxygen-bearing gases; transferring the titanium coated wafer to a sealed annealing chamber without substantially exposing the newly formed titanium layer to oxygen-bearing gases; annealing the titanium-coated semiconductor wafer in a nitrogen-bearing atmosphere in the sealed annealing chamber, and in the substantial absence of oxygen-bearing gases, at an annealing temperature of from 400.degree. C. up to below about 650.degree. C. to form a titanium nitride compound on the wafer; and further annealing the wafer at a temperature of from about 800.degree. C. to about 900.degree. C. to form a stable phase of stoichiometric titanium nitride (TiN) on the wafer.

Abstract: A plastic encapsulated integrated circuit package is disclosed which comprises a multilayer ground plane assembly bonded to a lead frame with an integrated circuit die bonded to the composite assembly. The multilayer ground plane assembly is first formed by bonding together a copper sheet and a thermally conductive polyimide material insulating layer to which is also bonded a layer of a b-stage epoxy resin. The ground plane assembly is then bonded to the lead frame by placing the b-stage epoxy layer of the ground plane assembly against the lead frame and heating the ground plane assembly and lead frame to a temperature of from about 120.degree. C. to just under 200.degree. C. for a time period not exceeding about 10 seconds to bond the b-stage epoxy resin to the lead frame without oxidizing it. An integrated circuit die is then attached to the composite assembly with an epoxy adhesive and the die attached assembly is then cured in a nonoxidizing atmosphere in an oven at approximately 150.degree. C.

Abstract: A hydrocarbon fuel is provided with one or more fullerene additives such as, for example, C60, C70, C74, C76, C78, C82, and C84 fullerenes, to serve as an identifying means for the fuel. The particular fullerene additive or additives may varying from the fullerene additive or additives in other fuels both by type as well as by amount or concentration present in the fuel. Thus, for example, if 7 different fullerenes are used in combinations of 1, 2, or 3 fullerenes, and in 5 different concentration amounts, there exists a possibility of as many as 4,935 different combinations of fuels which may all be separately identified by the presence of such combinations of fullerenes therein.

Abstract: A process is disclosed for the removal of residual oxide and/or silicon materials from a semiconductor wafer such as silicon-rich oxide residues or polysilicon stringers from the sidewalls of lines or steps formed over semiconductor wafers during the construction of integrated circuit structures without removing the wafer from the vacuum apparatus used in forming the lines on the wafer using a high pressure magnetically enhanced plasma etch using an NF.sub.3 -containing gas containing at least about 40 volume % NF.sub.3 as the etchant gas.

Abstract: A low temperature process is described for forming a coating or powder comprising one or more metals or metal compounds by first reacting one or more metal reactants with a halide-containing reactant to form one or more reactive intermediates capable of reacting, disproportionating, or decomposing to form a coating or powder comprising the one or more metal reactants. When one or more metal compounds are formed, either as powders or as coatings, a third reactant may be injected into a second reaction zone in the reactor to contact the one or more reactive intermediates formed in the first reaction zone to thereby form one or more metal compounds such as metal nitrides, carbides, oxides, borides, or mixtures of same.

Abstract: A process is described for removing from an integrated circuit structure photoresist remaining after a metal etch which also removes or inactivates a sufficient amount of any remaining chlorine residues remaining from the previous metal etch to inhibit corrosion of the remaining metal for at least 24 hours. The process includes a first stripping step associated with a plasma, using either O.sub.2 gas and one or more fluorocarbon gases, or O.sub.2 gas and N.sub.2 gas; followed by a subsequent step using a combination of H.sub.2 O.sub.2 /H.sub.2 O vapors, O.sub.2 gas, and optionally N.sub.2 gas associated with a plasma. Preferably, the plasma is generated in a microwave plasma generator located upstream of the stripping chamber, and the stripping gases pass through this generator so that reactive species produced from the gases in the plasma enter the stripping chamber.

Abstract: An apparatus is disclosed for removing one or more materials deposited on the backside and end edges of a semiconductor wafer which includes means for urging the front side of the wafer against a faceplate in a vacuum chamber; means for flowing one or more gases through a space maintained between the front side of the wafer and the faceplate; and means for forming a plasma in a gap maintained between the backside of the wafer and susceptor to remove materials deposited on the backside and end edge of the wafer; the gas flowing through the space between the front side of the wafer and the faceplate acting to prevent the plasma from removing materials on the front side of the wafer.

Abstract: An improved process is disclosed for the removal of deposits such as tungsten or tungsten silicide from a susceptor in a vacuum deposition chamber without leaving fluorine residues by first flowing a gaseous source of fluorine into a vacuum deposition chamber and igniting a plasma in the chamber while the gaseous source of fluorine is flowing therein to remove the depositions followed by flowing a gaseous source of hydrogen into the chamber and maintaining a plasma in the chamber during the flow of the gaseous source of hydrogen to remove any fluorine residues from the chamber.

Abstract: A method is described for making a multilayer lead frame assembly for an integrated circuit die package comprising a planar metal lead frame; at least one layer of insulating tape, provided with a b-stage adhesive on each surface thereof; and a planar metal member capable of functioning as a ground plane layer and as a heat sink. The method comprises: bonding the planar metal lead frame, one or more insulating tapes, and planar metal member together as a multilayer lead frame assembly prior to mounting the integrated circuit die to the resulting multilayer lead frame assembly. The planar metal member and planar lead frame are respectively bonded to a surface of the insulating tape by bringing the metal member (or lead frame) into contact with the b-stage adhesive on the surface of the insulating tape and then heating the metal member (or lead frame) and the insulating tape to the curing temperature of the b-stage adhesive to bond the metal member (or lead frame) to the insulating tape.

Abstract: A planarizing process for planarizing an integrated circuit structure in a CVD apparatus is disclosed using a low melting inorganic planarizing material which comprises flowing white depositing a low melting inorganic planarizing layer such as a boron oxide glass over a layer of insulating material such as an oxide of silicon, then dry etching the low melting inorganic planarizing layer to planarize the structure, and then depositing a further layer of an insulating material to encapsulate any remaining portions of the low melting glass planarizing layer which may be hygroscopic. The method eliminates the need for separate coating, drying, and curing steps associated with the application of organic-based planarizing layers usually carried out outside of a vacuum apparatus. In a preferred embodiment, the deposition steps and the etching step are all carried out without removing the integrated circuit structure from the apparatus.

Abstract: A process is described for inhibiting the vaporization or sublimation of aluminum base alloy surfaces when exposed to temperatures in excess of 400.degree. C. in a vacuum chamber used for the processing of semiconductor wafers. The process comprises treating such aluminum base alloy surfaces with a plasma comprising a nitrogen-containing gas selected from the group consisting of nitrogen and ammonia. When nitrogen gas is used, the plasma must also contain hydrogen gas. When the vacuum chamber being treated is intended to be used for the deposition of tungsten, the maximum flow of the nitrogen-containing gas into the chamber for the initial 10 seconds of the treatment process must be controlled to avoid impairment of the subsequent tungsten depositions in the chamber. After the treatment step, the cleaned and treated aluminum surface is preferably passivated with nitrogen (N.sub.2) gas.

Abstract: A process is described for removing, from an integrated circuit structure, photoresist remaining after one or more metal etch steps which also removes or inactivates a sufficient amount of remaining chlorine-containing residues from the previous metal etch steps to inhibit corrosion of remaining metal for at least 24 hours. The process includes a first stripping step which comprises flowing NH.sub.3 gas through a microwave plasma generator into a stripping chamber which contains the integrated circuit structure while maintaining a plasma in the plasma generator. O.sub.2 gas (and optionally NH.sub.3 gas) is flowed through the plasma generator into the stripping chamber during a second step while maintaining the plasma in the plasma generator.

Abstract: A process for the formation of an epitaxial layer on a semiconductor wafer is described which inhibits the formation of thermal stress in the semiconductor wafer such as a silicon wafer, during the formation of such an epitaxial layer thereon. In one aspect, such thermal stress is inhibited during the deposition of the epitaxial material by initially reducing the deposition rate to less than 1 .mu.m per minute or lower until the epitaxial layer reaches a thickness of from about 2 to about 30 .mu.m. In another aspect of the invention, any bridge materials formed between the wafer and the wafer support, during formation of the epitaxial layer, is removed before the wafer is cooled, i.e., before such bridge materials can induce thermal stress in the wafer during the cooling of the wafer, by post etching the wafer with HCl etching gas after the epitaxial deposition.

Abstract: A method is disclosed for forming a N,N-dinitramide salt having the formula MN(NO.sub.2).sub.2 where M is a cation selected form the class consisting of a metal ion and a nitrogen-containing ion, which comprises contacting a carbamate with a nitrating agent to form an acidic dinitramide intermediate reaction product, and neutralizing the acidic dinitramide with a compound selected from the class consisting of ammonia (NH.sub.3), hydrazine (N.sub.2 H.sub.4), a primary amine having the formula RNH.sub.2, a secondary amine having the formula RR'NH, and a salt having the formula AX; where R and R' are the same or different 1-6 carbon alkyls, A is a metal ion or a nitrogen-containing ion, and X is an anion selected from the class consisting of fluoride, chloride, hydroxyl, carbonate, alkoxide, and carboxyl anion, to form the corresponding dinitramide salt.

Abstract: A corrosion-resistant protective coating on an aluminum substrate capable of withstanding corrosion attack by process halogen gases and plasmas is disclosed. The protective coating is formed by contacting an aluminum oxide layer on an aluminum substrate with one or more fluorine-containing gases at an elevated temperature. In a preferred embodiment, a high purity corrosion-resistant protective coating on an aluminum substrate capable of withstanding corrosion attack may be formed by first forming a high purity aluminum oxide layer on the aluminum substrate and then contacting the aluminum oxide layer with one or more high purity fluorine-containing gases at an elevated temperature to form the high purity corrosion resistant protective coating thereon.

Abstract: In an epitaxial reactor system using a vacuum pump which is connected to the reaction chamber by an exhaust line, particulate contaminants normally deposit in the exhaust line near its juncture with the reaction chamber. When the vacuum pump is isolated from the reaction chamber during a back-filling operation, these contaminants can be entrained in the currents of gas normally produced in the back-filling operation. A removable baffle having the shape of a truncated cone is placed in the exhaust line at its juncture with the reaction chamber to prevent these particles from re-entering the reaction chamber.

Abstract: An improved process for formation of a capacitor in a trench formed in a semiconductor wafer is disclosed. The improved process comprises selectively implanting oxygen through the bottom surface of the trench into the region of the wafer adjacent the bottom surface of the trench and through the surfaces at the top corners of the trench into regions of the wafer adjacent such surfaces at the top corners of the trench using a plasma formed in a plasma-assisted etching apparatus while maintaining a high negative DC bias on the wafer being implanted. Subsequent growth of oxide on the surfaces of the trench will cause the implanted oxygen to form additional oxide in the implanted regions of the wafer adjacent the bottom surface of the trench and adjacent the surface at the top corners of the trench to compensate for the lower oxide growth rates in these areas.

Abstract: An improved process is described for forming one or more vias through an insulation layer by plasma etching to an underlying metal layer without depositing etch residues, including metal sputtered from the underlying metal layer, onto the sidewalls of the vias, which comprises, in one embodiment, using in the gaseous etchant one or more 3-6 carbon fluorinated hydrocarbons having the formula C.sub.x H.sub.y F.sub.z, wherein x is 3 to 6, y is 0 to 3, and z is 2x-y when the fluorinated hydrocarbon is cyclic and z is 2x-y+2 when the fluorinated hydrocarbon is noncyclic. One or more other fluorine-containing gases may also be used as long as the 3-6 carbon fluorinated hydrocarbons comprise at least 10 volume % of the fluorine-containing gas mixture. The fluorinated hydrocarbon gas or fluorine-containing gas mixture also may be mixed with up to 90 volume % total of one or more inert gases to control the taper of the via walls.

Abstract: A process is described for removing from an integrated circuit structure photoresist remaining after a metal etch which also removes or inactivates a sufficient amount of any remaining chlorine residues remaining from the previous metal etch to inhibit corrosion of the remaining metal for at least 24 hours. The process includes a first stripping step using either O.sub.2 gas or a combination of O.sub.2 gas and N.sub.2 gas and/or a fluorocarbon gas associated with a plasma followed by a subsequent step using a combination of O.sub.2 and NH.sub.3 gases associated with a plasma. When fluorocarbon gas is used in the first stripping step, a flushing step may be used prior to introduction of the NH.sub.3 gas to flush out any remaining fluorocarbon gas. Preferably, the plasma is generated in a microwave plasma generator located upstream of the stripping chamber and the stripping gases pass through this generator so that reactive species produced from the gases in the plasma enter the stripping chamber.

Abstract: A composite BPSG insulating and planarizing layer is formed over stepped surfaces of a semiconductor wafer by a novel two step process. The composite BPSG layer is characterized by the absence of discernible voids and a surface which is resistant to loss of boron in a subsequent etching step. The two step deposition process comprises a first step to form a void-free BPSG layer by a CVD deposition using gaseous sources of phosphorus and boron dopants and tetraethylorthosilicate (TEOS) as the source of silicon; and then a second step to form a capping layer of BPSG by a plasma-assisted CVD deposition process while again using gaseous sources of phosphorus and boron dpoants, and TEOS as the source of silicon, to provide a BPSG cap layer having a surface which is non-hygroscopic and resistant to loss of boron by subsequent etching.