Abstract: Fine, sub-micron line features and patterns are created in a radiation sensitive resist layer on a semiconductor wafer by a beam of short wavelength gamma rays. The resist layer includes photoresist which is substantially chemically inactive in response to the gamma rays. The photoresist is either doped or covered with a material that absorbs gamma rays and in response emits secondary radiation of a different wavelength, preferably photons, that is actinic with respect to the photoresist. The resist layer enables using radiation sources having better resolving ability than conventional photolithographic sources to perform near-field and direct-write lithography.

Abstract: Changing (varying, irregular) resist thickness on semiconductor wafers having irregular top surface topography or having different island sizes, affects the percent reflectance (and absorption efficiency) of incident photolithographic light, and consequently the critical dimensions of underlying features being formed (e.g., polysilicon gates). A low solvent content resist solution that can be applied as an aerosol provides a more uniform thickness resist film, eliminating or diminishing photoresist thickness variations. A top antireflective coating (TAR) also aids in uniformizing reflectance, despite resist thickness variations. The two techniques can be used alone, or together. Hence, better control over underlying gate size can be effected, without differential biasing.

Abstract: A process is disclosed for curing a hydrogen silsesquioxane coating material to form SiO.sub.2 by first placing the coating material in a preheated furnace; igniting a plasma ignited in the furnace immediately after insertion of the coating material therein; then raising the temperature of the furnace up to a predetermined curing temperature, while still maintaining the plasma in the chamber; maintaining the coating material at the curing temperature until substantially all of the coating material has cured to form SiO.sub.2 ; and then extinguishing the plasma and cooling the furnace. In another embodiment, the coating material is cured, with or without the assistance of heat and a plasma, in an ultrahigh vacuum, i.e., a vacuum of at least 10.sup.-5 Torr or better, and preferably at least 10.sup.-6 Torr or better.

Abstract: Changing (varying, irregular) resist thickness on semiconductor wafers having irregular top surface topography or having different island sizes, affects the percent reflectance (and absorption efficiency) of incident photolithographic light, and consequently the critical dimensions of underlying features being formed (e.g., polysilicon gates). A low solvent content resist solution that can be applied as an aerosol provides a more uniform thickness resist film, eliminating or diminishing photoresist thickness variations. A top antireflective coating (TAR) also aids in uniformizing reflectance, despite resist thickness variations. The two techniques can be used alone, or together. Hence, better control over underlying gate size can be effected, without differential biasing.

Abstract: An improvement in a sputter deposition apparatus and process for sputtering is described wherein the surface of the sputtering target, adjacent its outer edge, is provided with a taper which reduces the redeposition rate thereon of back scattered atoms previously sputtered from the target surface. When the sputtering apparatus includes a magnetron, the modified target acts to decrease the distance of the ions in the plasma from the magnetron to thereby increase the deposition rate adjacent the tapered portion of the target. The angle of the tapered portion of the target, with respect to the central portion of the target surface, must be at least about 30.degree., and preferably varies from about 35.degree. to about 70.degree., and most preferably from about 40.degree. to about 60.degree..

Abstract: A method for purging a vacuum chamber suitable for use in the production of integrated circuit structures on semiconductor wafers. The method comprises providing the chamber to be purged and flowing a heated, non-reactive gas, such as argon gas, through the chamber. The non-reactive gas is heated to a temperature of at least 90.degree. C. Further, the chamber is heated to maintain it at a temperature of at least 90.degree. C. while flowing the gas therethrough. Flowing the heated non-reactive gas through the chamber causes released impurities or contaminants to be efficiently swept from the chamber in the non-reactive gas flow. After flowing the heated gas through the heated chamber, the flow of gas is interrupted and the chamber, while still hot, is pumped down to a vacuum of about 5.times.10.sup.-7 to determine whether or not the chamber has a leakage problem.

Abstract: A process and apparatus is described for the processing of thin films on semiconductor substrates using one or more liquid precursor sources wherein the liquid precursor source with the highest vapor pressure is first vaporized and then introduced as a vapor into a common manifold connected to a processing chamber, with the point of introduction being spaced away from the processing chamber. A second liquid precursor source, having a vapor pressure lower than the first liquid precursor source, is then introduced in vaporized form into the manifold at a point closer to the processing chamber. This is repeated for each liquid precursor source, with each succeeding liquid precursor source having the next lower vapor pressure being introduced in vaporized form into the manifold at a point closer to the processing chamber than the previous liquid precursor source.

Abstract: A compact MOS type active device is constructed at least partially in an opening in an insulation layer, such as an oxide layer, above a portion of a semiconductor substrate forming a first source/drain region of the MOS type active device. A semiconductor material, on the sidewall of the opening, and in electrical communication with the portion of the substrate forming the first source/drain region of the device, comprises the channel portion of the MOS device. A second source/drain region, in communication with an opposite end of the channel, is formed on the insulation layer adjacent the opening and in electrical communication with the channel material in the opening. A gate oxide layer is formed over the channel portion and at least partially in the opening, and a conductive gate electrode is then formed above the gate oxide.

Abstract: A compact MOS type active device is constructed at least partially in an opening in an insulation layer, such as an oxide layer, above a portion of a semiconductor substrate forming a first source/drain region of the MOS type active device. A semiconductor material, on the sidewall of the opening, and in electrical communication with the portion of the substrate forming the first source/drain region of the device, comprises the channel portion of the MOS device. A second source/drain region, in communication with an opposite end of the channel, is formed on the insulation layer adjacent the opening and in electrical communication with the channel material in the opening. A gate oxide layer is formed over the channel portion and at least partially in the opening, and a conductive gate electrode is then formed above the gate oxide. In this embodiment, the memory transistors are connected to the Vcc bus by resistors.

Abstract: A process is described for forming, over a silicon surface, a titanium nitride barrier layer having a surface of (111) crystallographic orientation. The process comprises: depositing a first titanium layer over a silicon surface; sputtering a titanium nitride layer over the titanium layer; depositing a second titanium layer over the sputtered titanium nitride layer; and then annealing the structure in the presence of a nitrogen-bearing gas, and in the absence of an oxygen-bearing gas, to form the desired titanium nitride having a surface of (111) crystallographic orientation and a sufficient thickness to provide protection of the underlying silicon against spiking of the aluminum. When an aluminum layer is subsequently formed over the (111) oriented titanium nitride surface, the aluminum will then assume the same (111) crystallographic orientation, resulting in an aluminum layer having enhanced resistance to electromigration.

Abstract: A conductive member is described with a surface of controlled roughness thereon which is useful in the construction of an integrated circuit structure. In a preferred embodiment, the conductive member is formed using a mixture of germanium and silicon which is then oxidized, resulting in the formation of a roughened surface on the germanium/silicon conductive member due to the difference in the respective rates of oxidation of the germanium and silicon. After oxidation of the conductive member, the oxide layer may be removed, leaving the roughened surface on the germanium/silicon conductive member. When an integrated circuit structure such as an EPROM is to be formed using this conductive member with a roughened surface, a further layer of oxide is then deposited over the roughened surface followed by deposition of a second layer of conductive material such as polysilicon or a germanium/silicon mixture, from which the control gate will be formed.

Abstract: A technique for improving the radiation hardness and hot-electron resistance of a CMOS integrated circuit is described whereby undesirable hydrogen ions may be vented through any holes, such as contact holes, in an overlying passivation layer by applying an elevated temperature and/or electrical bias to the integrated circuit die. The elevated temperature and electrical bias serve to accelerate the process by which hydrogen vents from the die. The elimination of unwanted hydrogen significantly reduces threshold shifts in the CMOS integrated circuit, providing greater radiation hardness and hot-electron resistance.

Abstract: Fine, sub-micron line features and patterns are created in a sensitized layer on a semiconductor wafer by a beam of low wavelength radiation, such as X-rays. The X-ray source emits very low wavelength radiation along a path towards a sensitized surface of a semiconductor wafer. An image mask substrate is disposed in the path of the radiation, and is provided with opaque material on a surface thereof, forming a pattern. The image mask is spaced sufficiently close to the wafer that radiation passing through the mask forms a corresponding pattern in the surface of the wafer. For X-ray radiation, the opaqueing material is gold, tungsten, platinum, barium, lead, iridium, rhodium, or the like.

Abstract: Disclosed is a process for the formation of a tungsten silicide layer on an integrated circuit structure of a semiconductor wafer mounted on a susceptor in a vacuum chamber, wherein the tungsten silicide layer is applied at a temperature of at least 500.degree. C. and the susceptor has an aluminum nitride surface. After the chamber has been cleaned with one or more fluorine-containing etchant gases, the improvement comprises depositing a layer of tungsten silicide on the surface of the susceptor prior to an initial deposition of tungsten silicide on a wafer mounted on the susceptor after cleaning with the fluorine-containing etchant gases.

Abstract: An integrated circuit structure vertically isolated electrically from the underlying substrate is formed in/on a single crystal semiconductor substrate, such as a silicon semiconductor wafer, by first implanting the substrate with a sufficient dosage of noble gas atoms to inhibit subsequent recrystallization of the semiconductor lattice in the implanted region during subsequent annealing, resulting in the formation of an isolation layer comprising implanted noble gas atoms enmeshed with semiconductor atoms in the substrate which has sufficient resistivity to act as an isolation layer. The preferred noble gases used to form such isolation layers are neon, argon, krypton, and xenon. When neon atoms are implanted, the minimum dosage should be at least about 6.times.10.sup.15 neon atoms/cm.sup.2 to inhibit subsequent recrystallization of the silicon substrate. When argon atoms are implanted, the minimum dosage should be at least about 2.times.10.sup.15 argon atoms/cm.sup.2.

Abstract: A process for dynamically adjusting the concentration of one or more reactants in a plasma assisted press, such as a plasma etch process or a plasma deposition process, is describe. The concentration of one or more reactants, as well as the concentration of a non-reactive gas, in a plasma enhance process for the formation of an integrated circuit structure is quantitatively monitored by actinometry to derive a ratio of such concentrations of reactant to non-reactant. The concentration of the reactant or reactants in the plasma processing chamber is then maintained in the chamber by adjusting the flow of such reactant or reactants into the chamber based on changes in such ratio based on such continuous quantitative monitoring of the both the concentration of the reactant or reactants and that of the non-reactive (non-changing concentration) component.

Abstract: A process is disclosed for forming an integrated circuit device, such as an EPROM device, with a floating gate electrode with a discontinuous phase of metal silicide formed on a surface thereof is described. The process for forming such a discontinuous phase of metal silicide on the surface of a polysilicon floating gate electrode for the device comprises the steps of depositing a first polysilicon layer over a substrate, and preferably over a thin oxide layer on the substrate capable of functioning as a gate oxide; then forming a very thin layer of a silicide-forming metal over the polysilicon layer; and heating the structure sufficiently to cause all of the silicide-forming metal to react with the underlying polysilicon layer to form metal silicide and to coalesce the metal silicide into a discontinuous phase on the surface of the polysilicon layer.

Abstract: A plasma processing apparatus including a wafer supporting pedestal which is designed to reduce particle trapping phenomena. In a region of the pedestal surface which surrounds or abuts the wafer, the pedestal has a permittivity which is substantially equal to or greater than that of the wafer surface. As a result, the sheath boundary is reshaped to reduce particle trapping.

Abstract: A process is disclosed for pretreating aluminum-bearing surfaces in a vacuum deposition chamber after a previous step of cleaning the chamber, and prior to depositing tungsten silicide on substrates in the chamber, which first comprises treating the aluminum-bearing surfaces with a mixture of silane and a tungsten-bearing gas, such as WF.sub.6, to form a first deposition of a silane-based tungsten silicide on the aluminum-bearing surfaces. In a preferred embodiment, the process further comprises subsequently treating the already coated aluminum-bearing surfaces of the chamber in a second step with a mixture of a tungsten-bearing gas, such as WF.sub.6, and a chlorine-substituted silane such as dichlorosilane (SiH.sub.2 Cl.sub.2), monochlorosilane (SiH.sub.3 Cl), or trichlorosilane (SiHCl.sub.3) to form a chlorine-substituted silane-based tungsten silicide deposition over the previous deposited silane-based tungsten silicide.

Abstract: A process and resulting product are described for forming an integrated circuit structure with horizontal fuses on an insulation layer formed over other portions of the integrated circuit structure by forming rectangular recesses in the insulation layer which are subsequently filled during a subsequent metal deposition step which also serves to fill with the same metal vias or contact openings which have been etched through the insulation layer. Subsequent planarization of the deposited metal layer down to the vias or contact openings, i.e. to remove the portions of the metal layer over the insulation layer, leaves the metal in the vias or contact openings and also leaves metal stringers on the sidewalls of the rectangular recess which then serve as fusible links (fuses) which are then connected to one or more metal lines thereafter formed on the insulation layer.