Patents Represented by Attorney John P. Taylor
  • Patent number: 5470801
    Abstract: A low dielectric insulation layer for an integrated circuit structure material, and a method of making same, are disclosed. The low dielectric constant insulation layer comprises a porous insulation layer, preferably sandwiched between non-porous upper and lower insulation layers. The presence of some gases such as air or an inert gas, or a vacuum, in the porous insulation material reduces the overall dielectric constant of the insulation material, thereby effectively reducing the capacitance of the structure. The porous insulation layer is formed by a chemical vapor deposition of a mixture of the insulation material and a second extractable material; and then subsequently selectively removing the second extractable material, thereby leaving behind a porous matrix of the insulation material, comprising the low dielectric constant insulation layer.
    Type: Grant
    Filed: June 28, 1993
    Date of Patent: November 28, 1995
    Assignee: LSI Logic Corporation
    Inventors: Ashok K. Kapoor, Nicholas F. Pasch
  • Patent number: 5456952
    Abstract: A process is disclosed for curing a hydrogen silsesquioxane coating material to form SiO.sub.2 by first placing the coating material in a preheated furnace; igniting a plasma ignited in the furnace immediately after insertion of the coating material therein; then raising the temperature of the furnace up to a predetermined curing temperature, while still maintaining the plasma in the chamber; maintaining the coating material at the curing temperature until substantially all of the coating material has cured to form SiO.sub.2 ; and then extinguishing the plasma and cooling the furnace. In another embodiment, the coating material is cured, with or without the assistance of heat and a plasma, in an ultrahigh vacuum, i.e., a vacuum of at least 10.sup.-5 Torr or better, and preferably at least 10.sup.-6 Torr or better.
    Type: Grant
    Filed: May 17, 1994
    Date of Patent: October 10, 1995
    Assignee: LSI Logic Corporation
    Inventors: Mario Garza, Keith Chao
  • Patent number: 5453336
    Abstract: An improved rechargeable zinc cell is described comprising a zinc electrode and another electrode such as, for example, a nickel-containing electrode, and having an electrolyte containing one or more hydroxides having the formula M(OH), one or more fluorides having the formula MF, and one or more carbonates having the formula M.sub.2 CO.sub.3, where M is a metal selected from the group consisting of alkali metals. The electrolyte inhibits shape change in the zinc electrode, i.e., the zinc electrode exhibits low shape change, resulting in an improved capacity retention of the cell over an number of charge-discharge cycles, while still maintaining high discharge rate characteristics.
    Type: Grant
    Filed: January 26, 1994
    Date of Patent: September 26, 1995
    Assignee: Regents of the University of California
    Inventors: Thomas C. Adler, Frank R. McLarnon, Elton J. Cairns
  • Patent number: 5441918
    Abstract: A package for integrated circuit dies is disclosed comprising a ceramic base capable of having an integrated circuit die mounted to a central portion of one surface thereof to provide heat dissipation for the die; a lead frame with a central opening secured to the periphery of the same surface of the ceramic base; a raised frame member secured to both the lead frame and the peripheral portions of the same surface of the ceramic base exposed between the leads on the lead frame; a die mounted to the exposed central portion of the surface of the ceramic base surrounded by the lead frame and the raised frame member, and electrically bonded to leads on the lead frame; and a plastic potting material over and around the edges of the integrated circuit die and in contact with the exposed portion of the surface of the ceramic base adjacent the die, portions of the lead frame; and inner portions of the raised frame member to thereby encapsulate the integrated circuit die.
    Type: Grant
    Filed: November 8, 1993
    Date of Patent: August 15, 1995
    Assignee: LSI Logic Corporation
    Inventors: Maysayuki Morisaki, Hiroshi Matsumoto, Shoji Uegaki
  • Patent number: 5434044
    Abstract: A process is described for forming, over a silicon surface, a titanium nitride barrier layer having a surface of (111) crystallographic orientation. The process comprises: depositing a first titanium layer over a silicon surface; sputtering a titanium nitride layer over the titanium layer; depositing a second titanium layer over the sputtered titanium nitride layer; and then annealing the structure in the presence of a nitrogen-bearing gas, and in the absence of an oxygen-bearing gas, to form the desired titanium nitride having a surface of (111) crystallographic orientation and a sufficient thickness to provide protection of the underlying silicon against spiking of the aluminum. When an aluminum layer is subsequently formed over the (111) oriented titanium nitride surface, the aluminum will then assume the same (111) crystallographic orientation, resulting in an aluminum layer having enhanced resistance to electromigration.
    Type: Grant
    Filed: June 3, 1994
    Date of Patent: July 18, 1995
    Assignee: Applied Materials, Inc.
    Inventors: Jaim Nulman, Kenny K. Ngan
  • Patent number: 5432151
    Abstract: A process for depositing a biaxially aligned intermediate layer over a non-single crystal substrate is disclosed which permits the subsequent deposition thereon of a biaxially oriented superconducting film. The process comprises depositing on a substrate by laser ablation a material capable of being biaxially oriented and also capable of inhibiting the migration of substrate materials through the intermediate layer into such a superconducting film, while simultaneously bombarding the substrate with an ion beam. In a preferred embodiment, the deposition is carried out in the same chamber used to subsequently deposit a superconducting film over the intermediate layer. In a further aspect of the invention, the deposition of the superconducting layer over the biaxially oriented intermediate layer is also carried out by laser ablation with optional additional bombardment of the coated substrate with an ion beam during the deposition of the superconducting film.
    Type: Grant
    Filed: July 12, 1993
    Date of Patent: July 11, 1995
    Assignee: Regents of the University of California
    Inventors: Richard E. Russo, Ronald P. Reade, Stephen M. Garrison, Paul Berdahl
  • Patent number: 5427686
    Abstract: A separation process is described for separating a known material from a mixture of materials (which may contain unknown materials) using displacement chromatography. The process comprises passing a mixture of materials, including a known material to be recovered, dissolved in a liquid carrier, if necessary, through a first packed column and into a second packed column until all of the known material has passed through the first column and has been loaded onto the stationary phase packing in the second column. A displacement agent, capable of being more strongly bound on the stationary phase packing in the second column than the known material, is then passed through the second column to displace from that column all of the materials in the mixture less strongly bound than the known material, and then to displace the known material from the second column.
    Type: Grant
    Filed: April 5, 1994
    Date of Patent: June 27, 1995
    Assignee: SRI International
    Inventor: William J. Asher
  • Patent number: 5427666
    Abstract: A novel method of in-situ cleaning a Ti target in a Ti+TiN anti-reflective coating process when such Ti and TiN deposition process are conducted in the same process chamber by the addition of a simple process step and without the use of a shutter.
    Type: Grant
    Filed: September 9, 1993
    Date of Patent: June 27, 1995
    Assignee: Applied Materials, Inc.
    Inventors: Mark A. Mueller, Xin Guo, John C. Egermeier
  • Patent number: 5420371
    Abstract: A process is described for carrying out the dehydrogenation or hydrogenation, including hydrogenolysis, of a hydrocarbon in the presence of one or more soluble fullerene catalysts which have been dissolved in the hydrocarbon (when the hydrocarbon is a liquid capable of dissolving the fullerene catalyst) or dissolved in a solvent which is also a solvent for the hydrocarbon (when the hydrocarbon either is not a liquid or is not a liquid which is a solvent for the fullerene catalyst). The use of a liquid catalyst, i.e., a dissolved fullerene catalyst, inhibits coking reactions to thereby inhibit formation of coke on a solid catalyst or catalyst support by elimination of nucleation points or growth regions for such coke formation.
    Type: Grant
    Filed: March 18, 1994
    Date of Patent: May 30, 1995
    Assignee: SRI International
    Inventors: Ripudaman Malhotra, Doris S. Tse, Donald F. McMillen
  • Patent number: 5417161
    Abstract: A process, apparatus, and composition are disclosed for forming a molded foamed polyurethane explosive block with pentaerythritol tetranitrate in a manner in which the generation of excessive exothermic heat is inhibited during the reaction to form the foamed polyurethane. In one aspect of the invention, the exothermic heat generation is controlled by the use of non-reactive filler materials. In a preferred embodiment, a monoammonium phosphate filler is used to further impart fire retardant properties to the resultant molded foam explosive block.
    Type: Grant
    Filed: February 23, 1993
    Date of Patent: May 23, 1995
    Assignee: SRI International
    Inventors: Mohsen Sanai, S. Thomas Gaines, Gary R. Greenfield
  • Patent number: 5415852
    Abstract: A method is disclosed for forming an ionically bonded dinitramide salt or acid useful as a stable oxidizer for solid fuel rocket propellant or explosive formulations is disclosed. The dinitramide salt is formed by the reaction of an N(alkoxycarbonyl)N-nitroamide and a nitronium-containing compound, at a temperature of from about +60.degree. C. to about -120.degree. C., followed by contacting the reaction mass with a base to form the dinitramide salt, or an alcohol to form the corresponding dinitramidic acid. The N(alkoxycarbonyl)N-nitroamide may be formed by first mixing the corresponding alkylcarbamate with an anhydride of one or more 1-20 carbon organic acids, then adding nitric acid to the reaction mixture. If the salt of the N(alkoxycarbonyl)N-nitroamide is to be formed, a base is then added until the pH reaches about 7-10. The nitronium-containing reactant may be a covalently bonded compound containing a NO.sub.2 -- group; a nitryl halide; or a nitronium salt having the formula (NO.sub.2.sup.+).sub.q X.
    Type: Grant
    Filed: October 30, 1992
    Date of Patent: May 16, 1995
    Assignee: SRI International
    Inventors: Robert J. Schmitt, Jeffrey C. Bottaro, Paul E. Penwell, David C. Bomberger
  • Patent number: 5411593
    Abstract: A process and apparatus is disclosed for providing access to the interior of a vacuum deposition chamber in a vacuum deposition apparatus without exposing residues, such as chlorosilane residues, within the chamber to moisture and/or oxygen-containing gases. The process comprises first placing over the upper surface of the vacuum deposition apparatus an enclosure which has a bottom opening large enough to completely cover the top opening to the chamber, and which is capable of being filled with one or more non-reactive gases. One or more non-reactive gases are then flowed into the enclosure to purge moisture and/or oxygen-containing gases from the enclosure. After the enclosure has been mounted on the apparatus and purged by the flow of non-reactive gases therein, the vacuum deposition chamber may be opened, while continuing the flow of non-reactive gases into the enclosure.
    Type: Grant
    Filed: December 14, 1993
    Date of Patent: May 2, 1995
    Assignee: Applied Materials, Inc.
    Inventors: David K. Carlson, Norma B. Riley
  • Patent number: 5393712
    Abstract: A process is described for forming a low dielectric constant insulation layer on an integrated circuit structure on a semiconductor wafer by first forming a composite layer, comprising one or more extractable materials and one or more matrix-forming insulation materials, over an integrated circuit structure on a semiconductor wafer, and then selectively removing the extractable material from the matrix-forming material without damaging the remaining matrix material, thereby leaving behind a porous matrix of the insulation material. In one embodiment, the composite layer is formed from a gel. The extractable material is removed by first dissolving it in a first liquid which is not a solvent for the matrix-forming material to form a solution. This solution is then removed from the matrix-forming material by rinsing the matrix in a second liquid miscible with the first solvent and which also is not a solvent from the matrix-forming material.
    Type: Grant
    Filed: June 28, 1993
    Date of Patent: February 28, 1995
    Assignee: LSI Logic Corporation
    Inventors: Michael D. Rostoker, Nicholas F. Pasch, Ashok K. Kapoor
  • Patent number: 5391505
    Abstract: A compact MOS type active device is constructed at least partially in an opening in an insulation layer, such as an oxide layer, above a portion of a semiconductor substrate forming a first source/drain region of the MOS type active device. A semiconductor material, on the sidewall of the opening, and in electrical communication with the portion of the substrate forming the first source/drain region of the device, comprises the channel portion of the MOS device. A second source/drain region, in communication with an opposite end of the channel, is formed on the insulation layer adjacent the opening and in electrical communication with the channel material in the opening. A gate oxide layer is formed over the channel portion and at least partially in the opening, and a conductive gate electrode is then formed above the gate oxide.
    Type: Grant
    Filed: November 1, 1993
    Date of Patent: February 21, 1995
    Assignee: LSI Logic Corporation
    Inventor: Ashok K. Kapoor
  • Patent number: 5384008
    Abstract: A process and apparatus is described for depositing a layer of material over the entire frontside surface of a semiconductor wafer without leaving residues on the backside of said wafer. A semiconductor wafer is placed on the surface of a first wafer support without contacting the frontside surface of the wafer to thereby permit access by deposition materials to the entire frontside surface of the wafer, and then a layer of material is deposited on the entire frontside surface of the semiconductor wafer. To remove any deposits formed on the backside of the wafer during such a deposition, the coated wafer is then placed generally coaxially on the surface of a generally circular second wafer support which will permit access to the outermost portions of the backside of the wafer. In one embodiment the second wafer support is provided with an annular groove coaxially formed in the surface of the second wafer support which faces the backside of the wafer.
    Type: Grant
    Filed: June 18, 1993
    Date of Patent: January 24, 1995
    Assignee: Applied Materials, Inc.
    Inventors: Ashok Sinha, Sasson Somekh
  • Patent number: 5382316
    Abstract: A plasma etch process is described for simultaneously removing photoresist and etch residues, such as silicon oxide residues, remaining on a substrate from a prior polysilicon and/or polycide etch. The process comprises: (a) generating radicals in a plasma generator upstream of an etch chamber, from an etch gas mixture comprising (i) oxygen, water vapor, or a mixture of same; and (ii) one or more fluorine-containing etchant gases; and (b) then contacting the substrate containing the photoresist and residues from the previous polysilicon/polycide etch with the generated radicals in the etch chamber to remove both the photoresist and the etch residues during the same etch step.
    Type: Grant
    Filed: October 29, 1993
    Date of Patent: January 17, 1995
    Assignee: Applied Materials, Inc.
    Inventors: Graham W. Hills, Ruth E. Bucknall
  • Patent number: 5367051
    Abstract: Fullerene-functionalized amine-containing polymers and polymerizable monomers are disclosed characterized by high temperature stability, i.e., capable of withstanding a temperature of at least about 300.degree. C., and in some instances as high as 650.degree. C., when in polymerized form. The fullerene groups are bonded to the polymers through the amine groups on the polymer. In some instances enhanced mechanical properties also result and, in the case of cross-linked polymers, a composite can be formed from such materials which is structurally reinforced at the molecular level, with the fullerene groups acting as the molecular level structural reinforcement.
    Type: Grant
    Filed: July 22, 1993
    Date of Patent: November 22, 1994
    Assignee: SRI International
    Inventors: Subhash C. Narang, Susanna C. Ventura, Sivapackia Ganapathiappan, Tilak R. Bhardwaj, Asutosh Nigam
  • Patent number: 5360996
    Abstract: A process is described for forming, over a silicon surface, a titanium nitride barrier layer having a surface of (111) crystallographic orientation. The process comprises: depositing a first titanium layer over a silicon surface; sputtering a titanium nitride layer over the titanium layer; depositing a second titanium layer over the sputtered titanium nitride layer; and then annealing the structure in the presence of a nitrogen-bearing gas, and in the absence of an oxygen-bearing gas, to form the desired titanium nitride having a surface of (111) crystallographic orientation and a sufficient thickness to provide protection of the underlying silicon against spiking of the aluminum. When an aluminum layer is subsequently formed over the (111) oriented titanium nitride surface, the aluminum will then assume the same (111) crystallographic orientation, resulting in an aluminum layer having enhanced resistance to electromigration.
    Type: Grant
    Filed: May 21, 1993
    Date of Patent: November 1, 1994
    Assignee: Applied Materials, Inc.
    Inventors: Jaim Nulman, Kenny K. Ngan
  • Patent number: 5358886
    Abstract: An integrated circuit structure, and a method of making same is disclosed wherein one or more patternable busses of conductive material (such as polysilicon) interconnect electrode strips (such as gate electrode strips) of the same conductive material formed over active areas (such as MOS islands). The busses are formed on the structure over field oxide portions thereon during the initial step of patterning the layer of conductive material to expose the active areas and to form the electrodes thereover. After further processing to form other electrode regions in the active areas (e.g., source and drain regions in N-MOS and P-MOS islands), but prior to formation of an insulation layer over the structure for formation of a metal layer thereon, the busses are subjected to a further patterning step to form custom interconnections, as desired, between various electrodes in the integrated circuit structure.
    Type: Grant
    Filed: July 1, 1993
    Date of Patent: October 25, 1994
    Assignee: LSI Logic Corporation
    Inventors: Abraham Yee, Stanley Yeh, Tim Carmichael, Gobi Padmanabhan
  • Patent number: 5356835
    Abstract: An improved process is described for forming planar tungsten-filled contacts to a silicon substrate in contact openings through an insulating layer which provides for the formation of titanium silicide in and on the silicon surface at the bottom of the contact openings to provide low resistance silicide interconnections between the silicon substrate and the tungsten. A titanium nitride layer is formed over the titanium silicide and on the surfaces of the insulation layer, including the top surface of the insulation layer and the sidewall surfaces of the contact openings through the insulating layer. This titanium nitride layer provides a nucleation layer which permits a good bond to form from the tungsten through the titanium nitride and titanium silicide in the contact openings to the silicon substrate; and from the tungsten through the titanium nitride layer to the insulator material such as silicon dioxide (SO.sub.2), resulting in the formation of low resistance and low defect density contacts.
    Type: Grant
    Filed: June 16, 1993
    Date of Patent: October 18, 1994
    Assignee: Applied Materials, Inc.
    Inventors: Sasson Somekh, Jaim Nulman, Mei Chang