Abstract: Disclosed is an integrated circuit structure having one or more metal lines thereon with metal line sidewall retention structures formed on the sides of the metal lines. The metal line sidewall retention structures comprise a material sufficiently hard to inhibit lateral distortion or expansion of portions of the metal line during subsequent processing or use of the metal line. The metal line sidewall retention structures are formed by anisotropically etching a layer of a material sufficiently hard to inhibit lateral distortion or expansion of portions of the metal line after formation of a layer of such a material over and around the sides of the metal lines.

Abstract: Disclosed is a method of making an anodized aluminum susceptor capable of withstanding an elevated temperature of 590° C., or a temperature as high as 475° C. in the presence of an NF3 plasma, without peeling or cracking, which preferably comprises selecting a high purity or low magnesium aluminum alloy, roughening the surface of the alloy, and then anodizing the surface roughened alloy in an electrolyte comprising an organic acid to form the desired anodized aluminum oxide coating thereon. Further, the invention comprises a high purity or low magnesium aluminum alloy susceptor and an organic acid anodic coating thereon highly resistant to spalling or cracking at elevated temperatures.

Abstract: An integrated circuit structure is provided with a local interconnect layer and a first metal interconnect layer which are both capable of bridging over underlying conductive regions. The structure comprises a first dielectric layer formed to a height or thickness equal to or preferably exceeding the height of the highest conductive regions of the underlying integrated circuit devices; a second dielectric layer formed above the first dielectric layer; one or more local interconnects formed in the second dielectric layer; and a thin third dielectric layer formed over the second dielectric layer and the local interconnects therein. The thin third dielectric layer has a thickness not exceeding about 2000 Å, and preferably ranging from about 1000 Å to about 1500 Å. A first layer of metal interconnects is formed over the thin third dielectric layer.

Abstract: The invention comprises a process for forming a dielectric film having a compressive stress exhibited in the layers deposited onto an integrated circuit structure. This process includes depositing a first thin layer of dielectric material onto an integrated circuit structure, then exposing the integrated circuit structure to an elevated temperature. Then a second thin layer of dielectric material is deposited immediately overtop of the first thin layer of dielectric material, and then the integrated circuit structure is again exposed to an elevated temperature. The process is carried out to insure that the composite layer comprising the first and second deposited thin dielectric layers, after heat treatment, exhibits a residual stress which is compressive.

Abstract: A process for the formation of shaped Group II-VI semiconductor nanocrystals comprises contacting the semiconductor nanocrystal precursors with a liquid media comprising a binary mixture of phosphorus-containing organic surfactants capable of promoting the growth of either spherical semiconductor nanocrystals or rod-like semiconductor nanocrystals, whereby the shape of the semiconductor nanocrystals formed in said binary mixture of surfactants is controlled by adjusting the ratio of the surfactants in the binary mixture.

Abstract: A semiconductor processing apparatus and process is disclosed which is capable of degassing a semiconductor substrate and also orienting the substrate in the same vacuum chamber. The apparatus includes an electrostatic clamping structure for retaining the entire undersurface of a semiconductor substrate in thermal communication therewith in the vacuum chamber, a heater located within the electrostatic clamping structure for heating the electrostatically clamped substrate to degas it, a rotation mechanism for imparting rotation to the substrate in the vacuum chamber, and a detector for detecting the rotational alignment of the substrate in response to the rotation of the substrate. In a preferred embodiment, the substrate is rotated to rotationally align it as it is being heated to degas it.

Abstract: A method of making a metal interconnect stack for an integrated circuit structure is described comprising a main metal interconnect layer, an underlying TiN barrier layer and a titanium metal seed layer below the TiN barrier layer, and a barrier layer below the titanium metal seed layer to provide protection against chemical interaction between the titanium metal seed layer and an underlying plug in a via. The structure is formed by providing an integrated circuit structure having an insulation layer formed thereon with one or more metal-filled vias or contact openings generally vertically formed therethrough to have an upper surface thereon; forming a lower barrier layer such as a TiN barrier layer over the insulation layer and the upper surface of the metal in the one or more metal-filled vias; and subsequently forming the titanium seed layer over the lower TiN barrier layer.

Abstract: An integrated circuit structure is provided with an inductor formed therein which comprises a metal coil on an insulated surface over a semiconductor substrate, and a high magnetic susceptibility cobalt/nickel metal core located adjacent said metal coil, but spaced therefrom by one or more insulation layers. In one embodiment, the high magnetic susceptibility cobalt/nickel metal core is placed between lower and upper portions of the metal coil which are interconnected together by filled vias. In another embodiment, the metal coil is formed in a serpentine shape in one plane on an insulated surface over the semiconductor substrate, and the high magnetic susceptibility cobalt/nickel metal core is formed over the serpentine coil, but spaced from the serpentine coil by another insulation layer.

Abstract: An isolation trench in a silicon semiconductor substrate is provided with a barrier region containing nitrogen atoms formed in the trench, contiguous with the silicon semiconductor substrate surfaces of the trench. The novel isolation trench structure of the invention is formed by forming an isolation trench in a silicon semiconductor substrate; forming in the isolation trench a barrier region by treating the trench structure with nitrogen atoms from a nitrogen plasma; and then forming a silicon oxide layer over the barrier region in the trench to confine the nitrogen atoms in the barrier region. In a preferred embodiment, a silicon oxide liner is first formed over the silicon semiconductor substrate surfaces of the trench, and then the trench structure is treated with nitrogen atoms from a nitrogen plasma to form, on the silicon semiconductor substrate surfaces of the trench, a barrier layer which contains silicon atoms, oxygen atoms, and nitrogen atoms.

Abstract: The present invention provides apparatus and a process for efficiently removing particles generated during a laser marking of the semiconductor wafer substrate, thereby improving the yield. The process of the invention for marking a semiconductor wafer substrate by a beam of laser radiation comprises the steps of flowing a gas over a marking region at a predetermined flow rate and removing the gas from the marking region at the same predetermined flow rate, thereby generating a gas flow having a predetermined flow rate over and adjacent the marking region so that particles produced from the semiconductor wafer substrate while it is being marked will be removed. In a preferred embodiment, the semiconductor wafer substrate may be mounted with its upper surface to be marked directed downwardly while the laser marking beam is directed upwardly to the substrate.

Abstract: A composite metal line structure for an integrated circuit structure on a semiconductor substrate is disclosed which comprises: a low resistance metal core layer; a first thin protective layer of electrically conductive material on the upper surface of the metal core layer capable of protecting the metal core layer from reaction with tungsten; a layer of tungsten formed over the first protective layer to function as an etch stop layer for vias subsequently formed in an overlying dielectric layer; and a second thin protective layer of electrically conductive material over the tungsten layer and capable of functioning as an antireflective coating (ARC).

Abstract: A multiple well formation is provided in a CMOS region of a semiconductor substrate to provide enhanced latchup protection for one or more CMOS transistors formed in the wells. The structure comprises an N well extending from the substrate surface down into the substrate, a buried P well formed in the substrate beneath the N well, a second P well extending from the substrate surface down into the substrate, and an isolation region formed in the substrate between the N well and the second P well. The buried P well may extend beneath both the N well and the second P well in the substrate. In a preferred embodiment of the invention, the N well and the second P well are each implanted in the substrate at an energy level sufficient to provide a dopant concentration peak in the substrate below the depth of the isolation region to provide punch through protection and to provide a channel stop beneath the isolation region by proving a P-N junction between the N well and P well beneath the isolation region.

Abstract: Gaseous reactants capable of depositing a thin film on a semiconductor substrate are introduced into a deposition zone of a deposition apparatus through a gaseous reactants dispersion apparatus having rounded corners and smoothed anodized surfaces and maintained at a temperature ranging from about 70.degree. C. to about 85.degree. C., and preferably from about 75.degree. C. to about 80.degree. C., to inhibit the deposition and accumulation on such surfaces of charged materials capable of generating particles which may cause damage to the semiconductor substrate.

Abstract: A multiple step process sputter deposits material of uniform thickness on stepped surfaces of an integrated circuit substrate such as the surfaces of a high aspect ratio via or a narrow trench. Material is first sputter deposited at the bottom of the opening at high pressure using a source of high power RF energy connected to a coil in the deposition chamber to couple energy into the plasma. A high power RF bias is applied to the substrate, and a low power DC bias is applied to the sputtering target. The same parameters are repeated in a second step except that the high power RF bias on the substrate support is either reduced to a low power level or reduced to zero (by the end of the second step) to deposit on the lowest quarter of the sidewall of the opening. In a third step, no RF bias is applied to the pedestal remains and the pressure is reduced to a medium pressure state, resulting in a deposition on the second quarter of the sidewall of the opening.

Abstract: A crystalline semiconductor gate electrode having a re-entrant geometry and a process for making same are disclosed. The novel gate electrode may be formed from a polysilicon layer on a substrate by first implanting a masked polysilicon layer with a neutral species, i.e., a species which will not introduce a dopant into the polysilicon, such as a Group IV element, e.g., silicon, or a Group VIII element, e.g., argon. The neutral species is implanted into the masked polysilicon layer at an angle to provide a tapered implanted region which undercuts one side of the length (long dimension) of the mask. The substrate may then be rotated 180.degree. and then again implanted to provide a tapered implanted region which undercuts the opposite side of the length of the mask. When gate electrodes with such re-entrant geometry are to be formed on a substrate with their long axes at right angles to one another, i.e.

Abstract: Described is an improvement in a process wherein integrated circuit structures are formed on a front surface of a silicon substrate and at least one layer of copper is deposited on the front surface of the substrate to form a layer of copper interconnects, and wherein at least some copper is also deposited on the back surface of the substrate during this deposition. The improvement comprises: prior to the end of the formation of the integrated circuit structures, abrasively removing, from the backside of the substrate, copper deposited thereon during the deposition of copper on the front surface.

Abstract: A process is disclosed for forming vias and trenches in two separate dielectric layers, which may be separated by an etch stop, while avoiding the etch mask stress complicated resist masks, or high aspect ratio openings of the prior art. A first dielectric layer 10 is formed over an integrated circuit structure 2 on a semiconductor substrate, and a thin second dielectric layer 20 is formed over the first dielectric layer. A first resist mask, is formed over the second dielectric layer, and the first and second dielectric layers are etched through to form one or more vias 18, 28 extending through both the first and second dielectric layers. The first resist mask is then removed and a third dielectric layer 70, having different etch characteristics than the second dielectric layer, is deposited over the structure.

Abstract: An improved process is provided for amorphizing portions of a silicon substrate and a polysilicon gate electrode surface to be converted to metal silicide by subsequent reaction of the amorphized silicon with a metal layer applied over the silicon substrate and polysilicon gate electrode after the amorphizing step. The improvement comprises implanting the exposed surface of the silicon substrate and the surface of the polysilicon gate electrode with a beam of amorphizing ions at an angle of at least 15.degree. to a line perpendicular to the plane of the surface of the silicon substrate to thereby inhibit channeling of the implanted ions through the gate electrode to the underlying gate oxide and channel of the MOS structure. The implant angle of the beam of amorphizing ions is preferably at least 30.degree., but should not exceed 60.degree., with respect to a line perpendicular to the plane of the surface of the silicon substrate.

Abstract: The invention comprises an integrated circuit structure, and a process for making same, comprising a via/contact opening in a dielectric layer; a CVD layer of titanium nitride having a thickness of at least about 50 Angstroms, but not exceeding about 200 Angstroms, on the sidewall and bottom surfaces of the via/contact opening to provide adherence of the filler material to the underlying and sidewall surface of the opening; a CVD barrier layer of tungsten, having a thickness of about 50 Angstroms, but not exceeding about 300 Angstroms, formed over the titanium nitride layer; and the remainder of the via/contact opening filled with a highly conductive metal selected from the group consisting of copper, CVD aluminum, and force-filled aluminum.

Abstract: A luminescent semiconductor nanocrystal compound is described which is capable of linking to an affinity molecule. The compound comprises (1) a semiconductor nanocrystal capable of emitting electromagnetic radiation (luminescing) in a narrow wavelength band and/or absorbing energy, and/or scattering or diffracting electromagnetic radiation--when excited by an electromagnetic radiation source (of narrow or broad bandwidth) or a particle beam; and (2) at least one linking agent, having a first portion linked to the semiconductor nanocrystal and a second portion capable of linking to an affinity molecule.