Abstract: A process and resulting product are disclosed for an integrated circuit structure including two or more metal wiring levels interconnected by metal-filled vias. A first insulation layer, such as an oxide layer, is formed over a first metal wiring level on an integrated circuit structure. A via mask layer, such as a nitride mask layer, is then formed over the insulation layer with openings formed in the via mask layer in registry with portions of the underlying metal wiring to which it is desired to make electrical contact by the formation of vias through the first insulation layer. A second insulation layer, which may comprise a second oxide layer, is then formed over the mask layer. A reverse second metal wiring level mask, such as a photoresist mask or another nitride mask, is then formed over the second insulation layer to define the second metal wiring. The second insulation layer is then anisotropically etched with an etchant which is selective to the second level metal wiring mask and the via mask, i.e.

Abstract: A semiconductor processing apparatus and process is capable of degassing a semiconductor substrate and also orienting the substrate in the same vacuum chamber. The apparatus includes an electrostatic clamping structure for retaining the entire undersurface of a semiconductor substrate in thermal communication therewith in the vacuum chamber, a heater located within the electrostatic clamping structure for heating the electrostatically clamped substrate to degas it, a rotation mechanism for imparting rotation to the substrate in the vacuum chamber, and a detector for detecting the rotational alignment of the substrate in response to the rotation of the substrate. In a preferred embodiment, the substrate is rotated to rotationally align it as it is being heated to degas it.

Abstract: A process is described for forming self-aligned contacts to an MOS device on an integrated circuit structure characterized by the simultaneous formation of the metal silicide gate portion and the metal silicide source/drain portions. The process comprises forming a gate oxide layer on a silicon substrate, forming a polysilicon gate electrode layer over the gate oxide layer, and forming a layer of a first insulation material over the polysilicon gate electrode layer. Metal silicide is simultaneously formed on the exposed surface of the polysilicon gate electrode and over the exposed portions of the silicon substrate. Source/drain regions are formed in the silicon substrate, either before or after formation of the metal silicide over the exposed portions of the silicon substrate, whereby the metal silicide portions on the substrate above the source/drain regions are in electrical communication with the source/drain regions.

Abstract: An etch process selective to cobalt silicide is described for the selective removal of titanium and/or titanium nitride, unreacted cobalt, and cobalt reaction products other than cobalt silicide, remaining after the formation of cobalt silicide on an integrated circuit structure on a semiconductor substrate in preference to the removal of cobalt silicide. The first step comprises contacting the substrate with an aqueous mixture of ammonium hydroxide (NH.sub.4 OH) and hydrogen peroxide (H.sub.2 O.sub.2) to selectively remove any titanium and/or titanium nitride in preference to the removal of cobalt silicide. The second step comprises contacting the substrate with an aqueous mixture of phosphoric acid (H.sub.3 PO.sub.4), acetic acid (CH.sub.3 COOH), and nitric acid (HNO.sub.3) to selectively remove cobalt and cobalt reaction products (other than cobalt silicide) in preference to the removal of cobalt silicide.

Abstract: A process is disclosed for forming one or more doped regions beneath the surface of a single crystal semiconductor substrate, such as retrograde wells or deeper source/drain regions, by implantation at low energy which comprises orienting the crystal lattice of the semiconductor substrate, with respect to the axis of the implantation beam, i.e., the path of the energized atoms in the implantation beam, to maximize the number of implanted atoms which pass between the atoms in the crystal lattice. This results in the peak concentration of implanted atoms in the crystal lattice of the single crystal semiconductor substrate being deeper than the peak concentration of implanted atoms in the substrate would be if the axis of the implantation beam were not so oriented with respect to the crystal lattice of the semiconductor substrate during implantation.

Abstract: The formation of a cobalt silicide layer of uniform thickness over the source/drain regions and the polysilicon gate electrode of an MOS structure, which does not thin out adjacent the edges of the top surface of the polysilicon gate electrode, i.e., adjacent the oxide spacers, is achieved by first forming a titanium capping layer over a cobalt layer deposited over the MOS structure prior to formation of the cobalt silicide, and while excluding oxygen-bearing gases from the cobalt surface prior to the deposition of the titanium capping layer.

Abstract: A process for forming a photoresist mask over a patternable layer of an integrated circuit structure formed on a semiconductor substrate is described wherein the photoresist mask is initially formed with oversized lateral dimensions over a layer of patternable material of an integrated circuit on a semiconductor substrate. The oversized resist mask is then optionally measured in a vacuum apparatus to determine the size of the critical dimensions; then dry etched, preferably in the same vacuum apparatus, to reduce the size of the resist mask; then measured to determine the size of the critical dimensions (preferably again in the same vacuum apparatus); and then, if necessary, further dry etched to further reduce the size of the critical dimensions. The dry etching and subsequent measurement steps are repeated until the desired critical dimensions of the resist mask are reached.

Abstract: A novel integrated circuit structure, and process for making same, is disclosed wherein a tapered or gradient doped profile region is provided in a semiconductor substrate between the heavily doped drain region and the channel region in the substrate comprising an MOS device. In the process of the invention, a re-entrant or tapered gate electrode, resembling an inverted trapezoid, is used as a mask during a first doping step at a dosage level higher than normally used to form a conventional LDD region. This doping step forms a doped region having a dopant gradient which gradually increases in dosage level with distance from the channel region. Conventional oxide spacers may then be formed on the sidewalls of the gate electrode followed by conventional high level doping to form the heavily doped source and drain region in the unmasked portions of the substrate between the oxide spacers and the field oxide isolation.

Abstract: A process which is capable of forming shallow source/drain regions in a silicon substrate and a doped gate electrode by implantation of cobalt silicide contacts of uniform thickness previously formed on the substrate followed by diffusion of the dopant into the substrate to form the desired source/drain regions, and into the polysilicon gate electrode to provide the desired conductivity is described.

Abstract: A treated mesophase carbon fiber is disclosed having a high density of exposed edges on the fiber surface, and a method of making such a treated fiber. A carbon electrode is also described which is constructed from such treated mesophase carbon fibers. The resulting electrode, formed from such treated flexible carbon fibers, is characterized by a high density of active sites formed from such exposed edges, low corrosion, and good mechanical strength, and may be fabricated into various shapes. The treated mesophase carbon fibers of the invention are formed by first loading the surface of the mesophase carbon fiber with catalytic metal particles to form catalytic etch sites on a hard carbon shell of the fiber. The carbon fiber is then subject to an etch step wherein portions of the hard carbon shell or skin are selectively removed adjacent the catalytic metal particles adhering to the carbon shell.

Abstract: A method of providing etched alignment marks on a semiconductor workpiece that has a substantially planar surface, such as one that has been polished, for supporting accurate alignment of the workpiece in subsequent process operations. The surface of the semiconductor workpiece includes two layers of materials that abut at the workpiece surface. For example, the workpiece may include a layer of insulative material such as silicon dioxide forming several vias and a layer of conductive material such as tungsten forming plugs in the vias. The method includes etching the substantially planar surface to reduce a height of one of the materials below the height of the other material. For example, the tungstein plugs can be etched to a height that is below the height of the surrounding silicon dioxide. The location where the silicon dioxide abuts the tungsten produces a small bump. This bump then serves as an alignment mark for subsequent operations.

Abstract: A process for forming improved metal silicide contacts over the gate electrode and source/drain regions of MOS devices of an integrated circuit structure formed in a silicon substrate is described. The metal silicide contacts are formed by first forming a silicon oxide layer over exposed portions of the silicon substrate and over exposed surfaces of previously formed polysilicon gate electrodes. Silicon nitride sidewall spacers are then formed over the oxide on the sidewalls of the gate electrode by depositing a silicon nitride layer over the entire structure and then anisotropically etching the silicon nitride layer. Source/drain regions are then formed in the silicon substrate adjacent the nitride spacers and the structure is then contacted with an oxide etch to remove oxide from the upper surface of the gate electrode and the substrate surface over the source/drain regions.

Abstract: A process and resulting structure are described for using a metal layer formed over an insulating layer as both the filler material to fill openings in the insulating layer and as the patterned metal interconnect or wiring harness on the surface of the insulating layer. The process includes the steps of forming a compressively stressed metal layer over an insulating layer having previously formed openings therethrough to the material under the insulating layer; forming a high tensile strength cap layer of material over the compressively stressed metal layer; and then heating the structure to a temperature sufficient to cause the compressively stressed metal layer to extrude down into the openings in the underlying insulating layer. The overlying cap layer has sufficient tensile strength to prevent or inhibit the compressive stressed metal layer from extruding upwardly to form hillocks which would need to be removed, i.e., by planarization.

Abstract: A uniformly doped polysilicon gate electrode of an MOS device forming a part of an integrated circuit structure on a semiconductor substrate is formed by first depositing a very thin layer of amorphous or polycrystalline silicon, e.g., from about 2 nm to about 10 nm, over a gate oxide layer. The thin layer of silicon layer is then exposed to a nitrogen plasma formed from N.sub.2 at a power level sufficient to break the silicon--silicon bonds in the thin layer of silicon, but insufficient to cause sputtering of the silicon to cause a barrier layer of silicon and nitrogen to form at the surface of the thin silicon layer. Further silicon, e.g., polysilicon, is then deposited over the barrier layer to the desired thickness of the polysilicon gate electrode. The gate electrode is then conventionally doped, i.e.

Abstract: Described is an portion of an integrated circuit structure formed on a semiconductor substrate which provides electrostatic discharge (ESD) protection, utilizing an SCR structure, and also inhibits latchup of the SCR structure. The integrated circuit structure comprises an ESD protection device and an adjoining driver section matched together so that the width dimension of the ESD protection device matches the sum of the length of the adjacent driver section plus twice the width of a doped portion of the substrate forming a guard ring surrounding the driver section. When the length dimension of the MOS structure of the driver section is so maximized by further repeating of the source/gate/drain regions, the physical width dimension of the MOS structure of the driver section may be reduced without reducing the effective width of the MOS structure of the driver section, i.e., the effective width of the MOS structure remains sufficient to permit the required amount of power to be handled by the driver section.

Abstract: A low temperature process is disclosed for forming metal suboxides on substrates by cathodic arc deposition by either controlling the pressure of the oxygen present in the deposition chamber, or by controlling the density of the metal flux, or by a combination of such adjustments, to thereby control the ratio of oxide to metal in the deposited metal suboxide coating. The density of the metal flux may, in turn, be adjusted by controlling the discharge current of the arc, by adjusting the pulse length (duration of on cycle) of the arc, and by adjusting the frequency of the arc, or any combination of these parameters. In a preferred embodiment, a low temperature process is disclosed for forming an electrically conductive metal suboxide, such as, for example, an electrically conductive suboxide of titanium, on an electrode surface, such as the surface of a nickel oxide electrode, by such cathodic arc deposition and control of the deposition parameters.

Abstract: A microwave near field microscope has a novel microwave probe structure wherein the probing field of evanescent radiation is emitted from a sharpened metal tip instead of an aperture or gap. This sharpened tip, which is electrically and mechanically connected to a central electrode, extends through and beyond an aperture in an endwall of a microwave resonating device such as a microwave cavity resonator or a microwave stripline resonator. Since the field intensity at the tip increases as the tip sharpens, the total energy which is radiated from the tip and absorbed by the sample increases as the tip sharpens. The result is improved spatial resolution without sacrificing sensitivity.

Abstract: A method, and resulting product, are disclosed for selectively forming polycrystalline silicon over exposed portions of a single crystal silicon substrate. The method includes inhibiting the formation of such polycrystalline silicon over adjacent silicon oxide surfaces; and the resulting product of such a process. The polycrystalline silicon is selectively deposited over the single crystal silicon substrate by first forming a thin layer of a lattice mismatched material over the single crystal silicon surface, and then depositing a layer of polycrystalline silicon over the lattice mismatched material. Preferably, the thin lattice mismatched layer comprises a silicon/germanium (SiGe) alloy.

Abstract: A process and apparatus are described for inhibiting, but not completely eliminating, the deposition of titanium nitride by MOCVD on the end edge of a semiconductor substrate which comprises directing toward such substrate end edge a flow of one or more deposition-inhibiting gases in a direction which substantially opposes the flow of process gases toward the end edges of the substrate. This flow of deposition-inhibiting gases toward the end edges of the substrate reduces the deposition of the titanium nitride at the end edge of the semiconductor substrate either by directing some of the flow of process gases away from such end edge of the substrate, or by locally diluting such process gases in the region of the deposition chamber adjacent the end edge of the substrate, or by some combination of the foregoing.

Abstract: LDD regions of a MOSFET device in an integrated circuit structure are formed in a semiconductor substrate, after formation of the source/drain regions of the MOSFET device by forming spacers on the sidewalls of the gate electrode prior to doping of the substrate to form source/drain regions by implantation and annealing/activating. The sidewall spacers are then removed, and the portion of the substrate exposed by removal of the spacers is then lightly doped to form the desired LDD regions in the substrate between the respective source/drain regions and a channel region of the substrate below the gate oxide. In this manner, the dopant used to form the LDD regions is not exposed to the heat used to anneal and activate the implanted source/drain regions.