Abstract: An integrated circuit structure is described wherein individual integrated circuit devices such as MOS or bipolar transistors are constructed on and in a semiconductor substrate and one or more layers of metal interconnects are constructed on and in a second substrate, preferably of similar thickness, and the two substrates are then aligned and bonded together to thereby provide electrical interconnections of individual integrated circuit devices on the semiconductor substrate with appropriate metal interconnects on the second substrate to provide the desired integrated circuit structure without, however, contributing unduly to the overall size of the integrated circuit structure comprising the die or chip.

Abstract: A semiconductor wafer processing system for processing wafers from a wafer storage cassette includes a wafer transfer chamber; a wafer storage elevator within the transfer chamber; one or more wafer processing chambers; and a wafer transfer apparatus for transferring a wafer between a standard storage cassette adjacent and outside the transfer chamber and the elevator, and between the elevator and the processing chamber. The storage chamber pressure varies between atmospheric when accepting wafers from outside, and a subatmospheric pressure when transferring wafers to or from a processing chamber. The transfer apparatus includes a robot arm; a thin flat wafer carrying blade at the leading end of the robot arm configured for engaging a wafer from the storage cassette or the elevator; and a wafer support tray configured for removable engagement with the blade and for engaging and positively positioning a wafer from the elevator, or a support pedestal within a processing chamber.

Abstract: A process and apparatus are described for patterning a masked metal layer to form a layer of metal interconnects for an integrated circuits structure which removes metal etch residues, while inhibiting or eliminating erosion of the photoresist mask, by providing an amplitude modulation of the RF bias power supplied to the substrate support of the substrate being etched. The amplitude modulation of the RF power superimposes short pulses of RF power of sufficient magnitude (pulse height) and of sufficient duration (pulse width) to remove metal etch residues as they form during the etch process without, however, eroding the photoresist etch mask during the etch process sufficiently to adversely impact the patterning of the metal layer.

Abstract: A process and structure are disclosed for inhibiting the channeling of dopant through the polysilicon gate electrode into a semiconductor substrate during implantation of source and drain regions in the substrate during the formation of MOS devices. After deposition over a semiconductor substrate of a polysilicon layer which will be subsequently patterned to form a gate electrode, an amorphous layer of silicon is formed over the polysilicon layer. This amorphous silicon layer is then treated with a material such as a nitrogen-bearing material capable of inhibiting grain growth and recrystallization of the amorphous silicon during subsequent high temperature processing. The amorphous silicon and polysilicon layers are subsequently conventionally patterned to form the gate electrode. The structure is then implanted without channeling of the dopant ions through the gate electrode into the underlying portion of the substrate where the channel of the MOS device will be formed.

Abstract: A multilevel gate array MOS-type integrated circuit structure is described wherein each source, drain, and gate electrode region in the integrated circuit structure is accessible directly through a contact opening formed normal to the plane of the underlying substrate through an overlying insulation layer.

Abstract: A novel method of in-situ cleaning a Ti target in a Ti+TiN anti-reflective coating process when such Ti and TiN deposition process are conducted in the same process chamber by the addition of a simple process step and without the use of a shutter.

Abstract: An MOS structure is disclosed which is provided with a trench in the substrate adjacent the channel region of the substrate, i.e., adjacent the area of the substrate over which the gate oxide and gate electrode are formed. The region of the substrate beneath the trench is lightly doped to provide a deeper LDD region in the substrate between the channel and the drain region so that electrons traveling through the channel to the drain region follow a path deeper in the substrate and farther spaced from the gate oxide in the region of the substrate between the source region and the drain region where high fields are encountered by electrons traveling through the channel from the source region to the drain region.

Abstract: A low dielectric insulation layer for an integrated circuit structure material, and a method of making same, are disclosed. The low dielectric constant insulation layer comprises a porous insulation layer, preferably sandwiched between non-porous upper and lower insulation layers. The presence of some gases such as air or an inert gas, or a vacuum, in the porous insulation material reduces the overall dielectric constant of the insulation material, thereby effectively reducing the capacitance of the structure. The porous insulation layer is formed by a chemical vapor deposition of a mixture of the insulation material and a second extractable material; and then subsequently selectively removing the second extractable material, thereby leaving behind a porous matrix of the insulation material, comprising the low dielectric constant insulation layer.

Abstract: Changing (varying, irregular) resist thickness on semiconductor wafers having irregular top surface topography or having different island sizes, affects the percent reflectance (and absorption efficiency) of incident photolithographic light, and consequently the critical dimensions of underlying features being formed (e.g., polysilicon gates). A low solvent content resist solution that can be applied as an aerosol provides a more uniform thickness resist film, eliminating or diminishing photoresist thickness variations. A top antireflective coating (TAR) also aids in uniformizing reflectance, despite resist thickness variations. The two techniques can be used alone, or together. Hence, better control over underlying gate size can be effected, without differential biasing.

Abstract: Fine, sub-micron line features and patterns are created in a sensitized layer on a semiconductor wafer by a beam of Gamma-radiation. A continuous stream of such radiation, such as provided by a pellet of Cobalt-60, is collimated into a fine beam by a tapered collimator, and is gated on and off by a shutter mechanism comprising a distortable-surface device and a beam-blocking device. The fine, collimated beam converts points in a gamma-radiation-sensitive layer on a semiconductor wafer. By moving the wafer relative to the beam (or vice-versa), patterns are created in the layer of radiation-sensitive layer for further processing a layer underlying the radiation-sensitive layer.

Abstract: A gas distribution plate for a semiconductor wafer process chamber has a symmetrical pattern of non-circular openings formed therein for the passage of gas therethrough. The smaller axis of the non-circular openings should be at least about 127 .mu.m (5 mils), and preferably at least about 254 .mu.m (10 mils), but less than about 762 .mu.m (30 mils), and preferably less than about 635 .mu.m (25 mils). The larger axis is greater than the smaller axis, preferably at least about 635 .mu.m (25 mils), and most preferably at least about 762 .mu.m (30 mils). At least some of the walls of the non-circular openings are preferably not perpendicular to the plane of the face of the gas distribution plate, but are rather slanted, at an angle of from at least 30.degree. to less than 90.degree., toward the center or axis of the outer face of the circular gas distribution plate which faces the wafer.

Abstract: Changing (varying, irregular) resist thickness on semiconductor wafers having irregular top surface topography or having different island sizes, affects the percent reflectance (and absorption efficiency) of incident photolithographic light, and consequently the critical dimensions of underlying features being formed (e.g., polysilicon gates). A low solvent content resist solution that can be applied as an aerosol provides a more uniform thickness resist film, eliminating or diminishing photoresist thickness variations. A top antireflective coating (TAR) also aids in uniformizing reflectance, despite resist thickness variations. The two techniques can be used alone, or together. Hence, better control over underlying gate size can be effected, without differential biasing.

Abstract: A process and resulting product are described for controlling the channeling and/or diffusion of a boron dopant in a P- region forming the lightly doped drain (LDD) region of a PMOS device in a single crystal semiconductor substrate, such as a silicon substrate. The channeling and/or diffusion of the boron dopant is controlled by implanting the region, prior to implantation with a boron dopant,, with noble gas ions, such as argon ions, at a dosage at least equal to the subsequent dosage of the implanted boron dopant, but not exceeding an amount equivalent to the implantation of about 3.times.10.sup.13 argon ions/cm.sup.2 into a silicon substrate, whereby channeling and diffusion of the subsequently implanted boron dopant is inhibited without, however, amorphizing the semiconductor substrate.

Abstract: Fine, sub-micron line features and patterns are created in a sensitized layer on a semiconductor wafer by a source of X-ray radiation. The X-ray source emits very low wavelength radiation along a path towards a sensitized surface of a semiconductor wafer. An image mask substrate is disposed in the path of the radiation, and is provided with a patterned opaque material on a surface of a substrate thereof. The substrate is formed of beryllium, which is robust and has a thermal coefficient of expansion closely conforming to that of common image mask carriers. Further, a wide variety of opaqueing materials adhere well to the beryllium substrate, and the substrate is relatively insensitive to moisture. The image mask is spaced sufficiently close to the wafer that radiation passing through the mask forms a corresponding pattern in the surface of the wafer. For X-ray radiation, the opaqueing material is gold, tungsten, platinum, barium, lead, iridium, rhodium, or the like.

Abstract: A semiconductor wafer processing system for processing wafers from a wafer storage cassette includes a wafer transfer chamber; a wafer storage elevator within the transfer chamber; one or more wafer processing chambers; and a wafer transfer apparatus for transferring a wafer between a standard storage cassette adjacent and outside the transfer chamber and the elevator, and between the elevator and the processing chamber. The storage chamber pressure varies between atmospheric when accepting wafers from outside, and a subatmospheric pressure when transferring wafers to or from a processing chamber. The transfer apparatus includes a robot arm; a thin flat wafer carrying blade at the leading end of the robot arm configured for engaging a wafer from the storage cassette or the elevator; and a wafer support tray configured for removable engagement with the blade and for engaging and positively positioning a wafer from the elevator, or a support pedestal within a processing chamber.

Abstract: Fine, sub-micron line features and patterns are created in a sensitized layer on a semiconductor wafer by a beam of Gamma-radiation. A continuous stream of such radiation, such as provided by a pellet of Cobalt-60, is collimated into a fine beam by a tapered collimator, and is gaged on and off by a shutter mechanism comprising a distortable-surface device and a beam-blocking device. The fine, collimated beam converts points in a gamma-radiation-sensitive layer on a semiconductor wafer. By moving the wafer relative to the beam (or vice-versa), patterns are created in the layer of radiation-sensitive layer for further processing a layer underlying the radiation-sensitive layer.

Abstract: A process and is described for forming a tungsten silicide layer on a semiconductor wafer in a deposition chamber which comprises mounting a wafer on a susceptor having a fixed outer diameter regardless of the diameter wafer thereon to be processed in said chamber, and flowing into a deposition chamber a mixture of gases, including dichlorosilane gas and a gaseous source of tungsten through a fixed gas inlet pattern formed in a fixed diameter inlet receptacle, whereby a constant gas flow will be maintained in the deposition chamber regardless of wafer diameter being processed to thereby provide uniform deposition conditions in the deposition chamber, independent of wafer diameter.

Abstract: A CMOS integrated circuit structure is disclosed having a patterned nitride passivation layer, wherein the nitride is patterned such that it does not overlie the thin gate oxide portions of one or more of the MOS devices. When protection against the effects of external radiation is desired, the thin gate oxide areas of the PMOS devices are left uncovered by the patterned nitride passivation layer. When protection is desired against the effects of internally generated "hot electrons", the thin gate oxide areas of the NMOS devices are left uncovered by the patterned nitride passivation layer.

Abstract: Improvements in a wafer support apparatus used for electrostatic clamping of a wafer to the wafer support, and a method of making same, are disclosed wherein a dielectric material, formed on the surface of a wafer support facing the wafer to facilitate the electrostatic clamping, has a protective coating formed over the dielectric material to provide protection to the dielectric material against chemical attack from chemicals used during the processing of the semiconductor wafer. In a preferred embodiment, the protective coating comprises an aluminum compound, such as an oxide of aluminum or aluminum nitride, having a thickness ranging from about 1 micron to about 30 microns, but not exceeding about 50% of the thickness of the dielectric material so as to not interfere with the electrostatic charge used for clamping the wafer to the wafer support.

Abstract: A semiconductor wafer processing system for processing wafers from a wafer storage cassette includes a wafer transfer chamber; a wafer storage elevator within the transfer chamber; one or more wafer processing chambers; and a wafer transfer apparatus for transferring a wafer between a standard storage cassette adjacent and outside the transfer chamber and the elevator, and between the elevator and the processing chamber. The environment of the storage chamber varies in pressure between atmospheric when accepting wafers from outside, and a subatmospheric pressure when transferring wafers to or from a processing chamber.