Abstract: A method for forming an HSG (hemispherical grain) layer on a storage electrode of a capacitor formed on a substrate is provided. The method includes a step of introducing a source gas into a reacting chamber to deposit a small amount of HSG nuclei on a conductive layer pattern of a capacitor electrode during a step of stabilizing the substrate temperature. After the substrate temperature is stabilized, a larger amount of source gas is introduced into the chamber to form additional HSG nuclei. Thereafter, a step of annealing is performed to form the HSG layer.

Abstract: In order to solve the aforementioned problems, the present-invention provides a semiconductor device having a multilayer interconnection structure, wherein an upper interconnection comprises a first metal layer composed of an aluminum alloy, which is formed over a lower interconnection, and a second metal layer formed over the first metal layer and composed of an aluminum alloy formed as a film at a temperature higher than that for the first metal layer. Another invention provides a semiconductor device having a multilayer interconnection structure, wherein a metal region composed of a metal different from an aluminum alloy is formed in a portion spaced by a predetermined distance in an extending direction of an upper interconnection from an end of a via hole defined in the upper interconnection composed of the aluminum alloy, which is electrically connected to a lower interconnection through the via hole.

Abstract: A semiconductor package device has a circuit board with upper and lower conductive metal patterns respectively formed on upper and lower surfaces of the circuit board, a cavity centrally formed in the lower surface, and an opening through the upper surface that is connected to the cavity. A semiconductor chip is attached to the lower surface of the circuit board by an adhesive so that bonding pads of the chip are exposed through the opening. The semiconductor chip is disposed entirely within the cavity of the circuit board. Plating layers formed on side surfaces of the circuit board are electrically interconnected to the upper and lower metal patterns. An encapsulant protects the electrical interconnection parts of the semiconductor device package.

Abstract: A semiconductor device adopting an interlayer contact structure between upper and lower conductive layers and a method of manufacturing the semiconductor device adopting the structure are provided. The lower conductive layer includes a first conductive layer and a first silicide layer stacked together. The upper conductive layer includes a second conductive layer doped with impurities and a second silicide layer stacked together. In the interlayer contact structure, the first and second conductive layers are in direct contact with each other. This decreases the contact resistance between the two conductive layers and improves the electrical properties of the device.

Abstract: In a semiconductor integral circuit having a transistor or an inverter, a leak current of the transistor or a through current of the inverter, respectively, or the like is reduced. The semiconductor integral circuit has an analog circuit which changes linearly the voltage of an input signal and causes the amount of a current flowing through the analog circuit to change in accordance with the change in the voltage of the input signal. The semiconductor integral circuit also has a logic circuit to which an input signal having a first or second voltage is input. This logic circuit outputs an output signal having the first or second voltage in response to the first or second voltage of the input signal. The absolute value of the threshold value of the MOS transistor of the analog circuit is set smaller than the absolute value of the threshold value of the MOS transistor of the logic circuit.

Abstract: In a non-volatile memory, memory cells have respective floating gates formed of a first polysilicon and respective control gates formed of a second polysilicon. Further, in the non-volatile memory, peripheral circuits include transistors having respective gates formed of the first polysilicon. In addition, a silicide layer is formed directly on the control gates of the memory cells and directly on the gates of the transistors.

Abstract: A method of forming an isolation trench in a semiconductor substrate includes the steps of sequentially depositing first and second insulating layers over the substrate, subsequently etching the second and first insulating layers to define active and non-active regions according to a patterned masking photoresist layer, excessively etching a part of the thickness of the substrate, removing parts of the first insulating layer by undercutting the sides of the non-active region so as to expose parts of the substrate in the active region, etching the substrate by using the second insulating layer as a trench patterned masking layer to form a trench in which the edges of the exposed parts of the substrate are rounded, depositing a third insulating layer on the bottom and side walls of the trench and the rounded parts of the substrate to repair the parts of the substrate damaged when forming the trench, depositing a fourth insulating layer over the second insulating layer so as to completely fill the trench, etchin

Abstract: A motion correction device for images recorded by a camcorder from incident light having an incident direction. The device comprises at least one of horizontal and vertical component pick-ups. Each component pick-up comprises a converter for converting light into electrical signals, and a thin transmitter-reflector for transmitting a portion of the incident light at substantially the incident direction and for reflecting a remaining portion of the incident light at a range of other directions such that substantially all the reflected light impinges on the converter. The thin transmitter-reflector may be a curved transmission mirror for focusing the reflected light on the converter or a flat transmitter-reflector with a condenser disposed between the thin transmitter-reflector and the converter for focusing the reflected light onto the converter.

Abstract: A computerized system for providing various sorts of information regarding the current progress in a mass production process, for the ultimate purpose to allow a manager in charge of the mass production process to use the information to decide various parameters influential for the following processes, the computerized system having a various function to analyze the current position in the mass production process.

Abstract: The Mo or MoW composition layer has the low resistivity less than 15 &mgr;&OHgr;cm and is etched to have a smooth taper angle using an Al alloy etchant or a Cr etchant, and the Mo or MoW layer is used for a wiring of a display or a semiconductor device along with an Al layer and a Cr layer. Since the Mo or MoW layer can be deposited so as to give low stress to the substrate by adjusting the deposition pressure, a single MoW layer can used as a wiring by itself. When contact holes are formed in the passivation layer or the gate insulating layer, a lateral etch is reduced by using a polymer layer, an etch gas system CF4+O2 can prevent the etch of the Mo or MoW alloy layer, and an etch gas SF6+HCl(+He) or SF6+Cl2(+He) can form the edge profile of contact holes to be smoothed.

Abstract: A semiconductor device has a stress reducing laminate. Grooves are formed on the surface of a material layer selected from a multilayer structure of the semiconductor device, for example, a conductive layer. The cross sections of the grooves are semicircular or semi-elliptic. The stress applied to the conductive layer having the grooves is divided into a vertical component and a horizontal component with respect to the surface of the conductive layer. Accordingly, the stress applied vertically to the conductive layer is reduced, making it is possible to prevent the conductive layer from cracking due to stress and to reduce the stress transmitted to material layers under the conductive layer.

Abstract: A method for manufacturing a liquid crystal display is provided.

Abstract: A semiconductor device is comprised of a first wire that has a plurality of via holes formed in the vicinity of an end thereof and that is connected to a conductor of a different layer through the via holes, and a plurality of slits that are provided parallel to the direction in which the first wire extends and that split the first wire into a plurality of second wires over a predetermined distance from the end thereof.

Abstract: A rotary vane combustion engine is provided that uses a hot wall combustion insert to provide the heat for combusting a fuel-air charge. The rotary vane combustion engine includes a rotor having a plurality of vanes, a stator enclosing the rotor to form a plurality of vane cells between the plurality of vanes, one or more intake ports for providing intake gas to the vane cells, a fuel source for mixing fuel with the intake gas to form a fuel-air charge having a fuel-to-air equivalence ratio, a hot wall combustion insert with an exposed surface provided on the stator for igniting the fuel-air charge during a combustion cycle and producing an exhaust gas, and one or more exhaust ports for removing the exhaust gas from one of the vane cells. The hot wall combustion insert provides the heat to combust the fuel-air charge, and operates on the gas over a wide area, rather than only at a point or a given line of contact.

Abstract: A semiconductor device capacitor has a storage electrode wherein the impurity concentration decreases from the bottom to the top thereof. The semiconductor device capacitor is formed on a lower structure of a semiconductor substrate burying a contact hole formed on the semiconductor substrate. The impurity concentration linearly or non-linearly decreases going upward from the bottom of the contact hole to the top of the storage electrode. A method of manufacturing the semiconductor device capacitor also provides that the storage electrode is formed such that the concentration of impurities decreases linearly or non-linearly going upward from the bottom toward the top.

Abstract: The present invention provides a semiconductor memory capable of achieving redundancy relief for column line failure in a stable manner while realizing greater capacity and higher integration. A column decoder circuit CD11 provided in the semiconductor memory is provided with fuse blocks FB(0)˜FB(127), first decoders DA(0)˜DA(127), redundancy control circuits RL(0)˜RL(127) and RLr, second decoders DB(0)˜DB(255), DBr(0) and DBr(1) and column line drivers DV11(0)˜DV11(255), DV11r(0) and DV11r(1). A redundancy control circuit RL(k) is connected with a column line driver DV11(2k) that drives a column line CL(2k) and a column line driver DV11(2k+1) that drives a column line CL(2k+1) via second decoders DB(2k) and DB2(2k+1) respectively.

Abstract: The present invention relates to a liquid crystal display having repair lines and methods of repairing defect in the same. The liquid crystal display comprises a plurality of gate lines in horizontal direction, a plurality of data lines perpendicular thereto, and a plurality of repair lines repeatedly formed corresponding to a fixed number of data lines. The repair line comprises an upper portion crossing top of the data lines, a lower portion crossing bottom of the data lines, and a middle portion which is parallel to the data line connecting the upper and the lower portions. A repair line is formed repeatedly for each data-line block which consists of data lines in any multiples of three. Under the above wiring structure, a disconnected data line is repaired by shorting the crossing points of the data line and the repair line corresponding to the data-line block of the disconnected data line.

Abstract: A vertical MOS semiconductor device in accordance with the present invention is provided with a semiconductor base; and a vertical MOS transistor having a well diffusion layer of a conductive type opposite to that of the semiconductor base, and a source diffusion layer of the same conductive type as that of the semiconductor base; wherein a channel length in a horizontal direction with respect to a main surface of the semiconductor base from a junction of the source diffusion layer to a junction of the well diffusion layer is set such that it is larger than a length at which a punch-through phenomenon takes place between the semiconductor base and the source diffusion layer and at which a minimum resistance value of the well diffusion layer is obtained. This arrangement makes it possible to reduce the size of the entire vertical MOS semiconductor device to 90% as compared with a conventional vertical MOS semiconductor device, without sacrificing a high breakdown voltage characteristic.

Abstract: A matrix-type display device having a repair layout, particularly, a matrix-type display device which can be repaired in a pixel unit, is provided. Two or more of signal lines such as scanning signal lines, displaying signal lines and auxiliary signal lines and a pixel electrode are overlapped via an insulating layer, so that a defect such as the disconnection of the displaying signal lines and scanning signal lines, the short of the pixel electrode and signal line, and the loss of electrode of a switching element, can be repaired. Here, the layout of the auxiliary gate line and dual gate line can be modified.

Abstract: The invention provides a semiconductor integrated circuit wherein a PMOS 111 having a high threshold voltage is installed between a VDD line 101 and a VDDV line 103, and a NMOS 121 having a high threshold voltage is installed between a VSS line 102 and a VSSV line 104. The semiconductor integrated circuit comprises a logic gate circuit supplied with a power source voltage via the VDDV line 103 and the VSSV line 104, respectively, and made up of PMOSes 131 to 133, and NMOSes 141 to 143. A substrate terminal of the PMOSes 131 to 133, respectively, is connected to a pad 163 to which a suitable voltage can be supplied from outside while a substrate terminal of the NMOSes 141 to 143, respectively, is connected to a pad 164 to which a suitable voltage can be supplied from outside. The semiconductor integrated circuit with such a configuration is capable of improving a failure detection ratio at testing.