Abstract: In addition to first and second control circuits, an I/O circuit has a first MOS transistor which includes a gate electrode connected to a first node to which a first signal is input from at least one of a first power supply and an internal circuit, a first electrode connected to the first power supply, and a second electrode connected to a second node. A second MOS transistor includes a gate electrode connected to a third node, a first electrode, a second electrode connected to a second node, and a substrate connected to a fourth node which is in a floating state. A third MOS transistor includes a gate electrode connected to the third node, a first electrode, a second electrode, and a substrate connected to the fourth node.

Abstract: A transfer molding apparatus, wherein a top-half mold and a bottom-half mold form a plurality of cavities interconnected, and wherein a pressure adjuster reduces the pressure of the cavities every time a specified amount of resin is supplied into any of the plurality of cavities.

Abstract: A back lapping in-line system for semiconductor device fabrication carries out a vinyl covering, a back side grinding, and a vinyl removing for grinding the back side of a wafer in-line with one single process. The back lapping in-line system has a server connected to a network line, a program therein for controlling the in-line processes, and an in-line facility connected to the server by a standard communication line, wherein parts of the in-line facility are assembled in order, and each part carries out its corresponding process according to information communicated to and from the server, and unloads the wafer after it passes through all of the corresponding processes successively. The in-line facility uses a single loading and unloading, and needs no storage space between parts.

Abstract: A method of fabricating a semiconductor device includes nitriding a native oxide layer on a pattern of polysilicon layers to be used as the lower electrode of a capacitor in LPCVD equipment at a constant temperature in an environment of ammonia gas. A nitride layer is then deposited onto the nitrided native oxide layer in the in-situ state. An oxide layer is then deposited onto the entire nitride layer, and thereafter a pattern of upper electrodes are formed on the oxide layer, thereby shortening the period of time required for forming the entire nitride layer of the NO dielectric layer without any deterioration in the product quality.

Abstract: An object of the invention is to provide a semiconductor memory which is not susceptible to the change of a threshold value caused by variations in a fabricating process. The semiconductor memory comprises a memory cell part, a voltage generation circuit for generating a substrate voltage of the memory cell part, a threshold value detection circuit for outputting threshold value detection signals in response to a threshold value of a transistor formed on the memory cell part, and a voltage detection circuit for detecting the substrate voltage generated by the voltage generation circuit, outputting a voltage detection signal at a given voltage in response to the threshold value detection signals to stop the operation of the voltage generation circuit.

Abstract: A method of fabricating a capacitor of a semiconductor device maximizes the imurity density of HSG formed at a surface of an electrode of the capacitor and thereby improves capacitance and breakdown voltage characteristics of a DRAM device incorporating the same. The method includes forming an inter-level insulating layer having a buried contact hole which exposes the underlying semiconductor substrate, forming an amorphous polysilicon layer doped with a low density of a p-type impurity on the resultant structure, selectively etching the polysilicon layer with a mask having a pattern configured to form a bottom electrode over a predetermined portion of the inter-level insulating layer which includes the contact hole, causing HSG to grow on the exposed surface of the bottom electrode, and doping PH3 into the HSG under a “low temperature/ high pressure” process condition.

Abstract: A compound semiconductor device is formed having a plurality of FETs exhibiting the same electrode ratio of a difference between a surface area of the active region and the combined overlapping surface area of the source and drain ohmic electrodes to the combined overlapping surface area of the source and drain ohmic electrodes. As such, precise control of a threshold voltage of the FETs is achieved. The compound semiconductor device is also formed so as to include a plurality of resistors having the same ratio of a difference between a surface area of the resistivity region and the combined overlapping surface area of the pair electrodes to the combined overlapping surface area of the pair electrodes. In this manner, a resistivity of the resistor is precisely controlled.

Abstract: A synchronous DRAM (SDRAM) having a posted column access strobe (CAS) latency and a method of controlling CAS latency are provided. In order to control a delay time from the application of a CAS command and a column address to the beginning of memory, reading or writing operations in units of clock cycles, a first method of programing the delay time as a mode register set (MRS) and a second method of detecting the delay time using an internal signal and an external signal, are provided. In the second method, the SDRAM can include a counter for controlling the CAS latency. This counter controls the CAS latency of the SDRAM by generating a signal for controlling the CAS latency according to the number of clock cycles of a clock signal from the generation of a row access command to a column access command in the same memory bank and reading the signal.

Abstract: Thinner compositions for effectively removing photoresist. The thinner compositions may be used in reworking a semiconductor substrate or in rinsing semiconductor devices. The thinner composition may be a mixture of n-butyl acetate (n-BA) and ethyl acetate (EA), a mixture of n-butyl acetate (n-BA) and methyl methoxy propionate (MMP), or a mixture of n-butyl acetate (n-BA) and methyl ethyl ketone (MEK).

Abstract: In a semiconductor device 1 according to the present invention, a plurality of inner leads are bonded to a front surface of a semiconductor element 11 covered by a package 10, with bent portions 17 formed at some inner leads 13a among the plurality of inner leads 13 and the front ends of the bent portions 17 exposed at a front surface of the package 10. This structure ensures that the semiconductor element is not caused to move vertically inside the forming die by the pressure of the liquid resin or the like during the sealing process.

Abstract: A semiconductor memory device for improving the transmission data rate of a data input and output bus, and a memory module including the same, are provided. The memory module includes a plurality of clock synchronous memory devices that share a single data bus line. More specifically, the memory module includes a printed circuit board having an electrical connector including the data bus line, a first set of synchronous memory devices arrayed on the printed circuit board, a second set of synchronous memory devices arrayed on the print circuit board, and a clock signal generator electrically connected to the first and second set of synchronous memory devices. The clock signal generator operates to receive a clock signal from the electrical connector and to generate a first clock signal that is matched with the received clock signal and a second clock signal that is delayed with respect to the received clock signal for half the period of the received clock signal.

Abstract: A sidewall passivation layer is deposited on an etched feature in a semiconductor substrate with a hydrocarbon deposition gas by introducing H2, determining certain mixture percentages for the hydrocarbon gas/H2 mix at which the etch rate for the substrate peaks, the etch rate begins to rise from a generally steady state, and/or the etch rate falls to zero, and then maintaining the mixture percentage within a selected range. Where the hydrocarbon gas/H2 mix is maintained at a percentage between the steady-state etch rate percentage and the peak etch rate percentage, then relatively high ion energies are used. Where the hydrocarbon gas/H2 mix is maintained at a percentage between the peak etch rate percentage and the percentage where the etch rate falls to zero, then relatively low ion energies are used.

Abstract: A memory circuit includes a memory cell array having word lines, bit lines and memory cells, and a word line reset circuit for applying an activation level to a word line that is selected, and for applying a lower level which is lower than a deactivation level to the word line when it is non-selected. The word line reset circuit includes a first driver for applying the activation level to the selected word line during a first selected period, a second driver for applying the deactivation level to the word line during a second select period after the first select period, and a third driver for applying the lower level to the word line during a period other than the first and second select periods.

Abstract: The present invention relates to a cyclone turbine flowmeter for extracting information about a flow rate or measuring the quantity of flow flowing in production facilities. The cyclone turbine flowmeter includes a cyclone turbine formed with flow channels for allowing liquids flowing in from the outside to receive rotary power, a rotor rotated by the liquids passed through the flow channels of the cyclone turbine, a turbine bearing manufactured so as to minimize frictional forces and at the same time, to have durability and resistance to chemicals, and a vibration isolation bearing constructed in such a manner of enclosing the turbine bearing and its turbine axle to prevent vibration.

Abstract: A software license control system is based on independent software registration servers. The registration servers are open to all software manufacturers. On user's computer, a software product asks the user software license control program whether the user has a usage license for the software product. The user license control program checks the license file, received from a software registration server, and answers the software product. If the answer is “no”, the software product stops running. If the answer is ‘yes’, the software product continues. The license file cannot be used by unauthorized user because the file is encrypted by the user public key and digitally signed by the secret key of a software registration server. To use a license file, user needs the secret key of the user and needs a passphrase to activate the secret key. The license file is digitally signed by the software registration server and cannot be modified by a user to add unauthorized licenses.

Abstract: A metal pattern 4 is formed at a rear surface of a substrate 3 at a front surface of which a molded semiconductor chip is mounted, the metal pattern 4 is covered with an insulating film 5 except at its connecting area 4a and a solder ball 6 is bonded to the connecting area 4a. The area of the metal pattern 4 other than the connecting area 4a inclines toward the substrate 3 and gradually becomes thinner toward the outside. Stress, which is applied to the solder ball 6, is imparted in a diagonal direction and is dispersed. As a result, the number of occurrences of cracks X is reduced and the solder ball which is used to achieve connection with an external substrate is effectively prevented from becoming electrically disconnected.

Abstract: A wafer processing chamber 11 includes a wafer support 12, a dielectyric window 13 and coaxial coils 15 and 16 located outside the dielectric window 13 for inducing a plasma within the chamber. A variety of coil/dielectric windows are described together with protocols for their control.

Abstract: A semiconductor device, and corresponding method of fabrication, includes a device isolation region formed in a semiconductor layer of a SOI substrate, the semiconductor layer having a first type of conductivity, a first impurity region made of portions of the semiconductor layer, and second and third impurity regions formed in the semiconductor layer outside of the first impurity region, the second and third impurity regions having a second type of conductivity. A base electrode is electrically connected to the first impurity region, a bit line electrode is electrically connected to the second impurity region and a capacitor is electrically connected to the third impurity region. The base electrode may be formed by etching a first contact hole through a first interlayer insulating film formed over the semiconductor layer and filling the first contact hole with an electrically conductive material.

Abstract: In a plastic packaged semiconductor device, a chip support formed on the same lead frame as leads is disposed so as to extend over the surface of a semiconductor element, the chip support is bonded and fixed to the surface of a polyimide wafer coat on the semiconductor element by means of an insulating tape, the leads are brought into contact with the polyimide wafer coat on the semiconductor element without being fixed, the leads and the electrodes of the semiconductor element are connected by means of gold wires, and these are packaged by a packaging material. Generation of crack in the sealing material thereby prevented, and the thickness of the plastic packaged semiconductor device is reduced.

Abstract: A method of fabricating a self-aligned stacked capacitor is provided, in which buried contacts and storage nodes are simultaneously formed by electroplating. In this method, a semiconductor substrate having exposed conductive areas is prepared for, and an interlayer insulative layer having buried contact holes that expose the conductive areas, is formed over the semiconductor substrate. A lower conductive seed layer is then formed over the entire surface of the innerwalls of the buried contact holes and the upper surface of the interlayer insulative layer. Non-conductor patterns having storage node holes that expose the buried contact holes, are then formed over the lower conductive seed layer on the upper surface of the interlayer insulative layer. A buried contact that fills the buried contact hole, and a lower electrode that fills the storage node hole, are then simultaneously formed by electroplating.