Abstract: A terminal connecting device includes a main body of a terminal block having diaphragms and supporting strips, a terminal plate positioned at the top of the supporting strips, movable terminals supported by a spring to attach or detach lead wire positioned on the terminal plate, a restraining structure, proximate to the movable terminals, which limits the movement of the lead wire, and a terminal screw coupled with the movable terminals after being penetrated through the through hole of the lead wire and fastened at a screw hole of the terminal plate. The restraining structure restricts the lead wire from diverting or dropping, thereby preventing safety accidents such as stopping the operation of facility or electric shock. The restraining structure also allows easy penetration of the terminal screw through the through hole of the lead wire in fixing the lead wire, thereby improving productivity due to ease of fastening the terminal screw.

Abstract: A semiconductor device includes a Schottky layer, a cap layer covering the surface of the Schottky layer, and a Schottky electrode of a two-level structure. The Schottky electrode has a lower portion that penetrates through the cap layer and reaches the Schottky layer, and has an upper portion larger than the lower portion in cross-sectional area and that overlies the cap layer. With this construction, surface defects are unlikely to occur, so that a highly reliable semiconductor device can be fabricated.

Abstract: With a construction wherein an interlayer insulating film of a semiconductor device is comprised of a TEOS oxide film formed by means of the plasma CVD method as an underlayer of the interlayer insulating film, and a TEOS oxide film formed by means of the CVD method as an upper layer of the same, laminated to the former, the thickness of the upper layer film is increased by changing an output in low frequency bands of RF, or changing a ratio of a TEOS gas flow rate to an O2 flow rate in applying the plasma CVD method to form the underlayer film.

Abstract: In a semiconductor memory capable of verifying data stored therein, a verification pass signal output from a verification circuit is input to a control signal output circuit. In the case of a normal mode operation of the control signal output circuit, a signal having a voltage level corresponding to that of the verification pass signal is output therefrom. In the case of a test mode operation of the control signal output circuit, a signal having a given voltage level regardless of voltage level of the verification pass signal is output therefrom. In cases where the signal having the given voltage level is output from the control signal output circuit, a write control circuit and a write counter execute a preset maximum number of program processings and verifications processing.

Abstract: In a semiconductor device comprising a resistance element electrically connected to a bipolar transistor, the bipolar transistor is formed on a silicon substrate and a predetermined resistance element is formed on an insulation film formed on the bipolar transistor based on results of measurements monitored for this transistor, in such a manner that the semiconductor device has prescribed characteristics.

Abstract: In a TiSi2 layer formation method in which a Ti layer is formed by a CVD method supplying TiCl4 gas together with a carrier gas at a prescribed temperature onto a Si layer and forming a TiSi2 layer by having the Ti layer react with the Si layer in a self-aligning manner, the TiCl4 gas is supplied at the flow rate proportion of over 0.5% of the total gas flow rate. Or, a halogen type gas such as HCl gas and Cl2 gas is added to the TiCl4 gas by the flow rate proportion of 0.05%˜1% of the flow rate of the TiCl4 gas. Or, after the Ti layer film is formed, the TiCl4 gas is supplied for a prescribed length of time without discharging plasma.

Abstract: A read-out circuit, includes a data detecting circuit which detects analog data of a selected memory cell; a data condition deciding circuit which decides whether or not the analog data detected by the data detecting circuit is in a normal range; and a controller which normalizes an output signal for the selected memory cell in accordance with the decision of the data condition deciding circuit.

Abstract: A mask for a selective growth of a solid, is provided in which the solid is selectively grown in a predetermined region of a substrate and growth on other regions is suppressed. A method is also provided for selectively growing a solid on only the predetermined region of a substrate using the mask. In the mask, a surface layer and an underlayer are provided, each having different chemical compositions. Thus, even if the mask is formed on a substrate in an ultra thin film, the generation of mask defects can be suppressed and stability provided to heat and electron beams.

Abstract: A system for supplying slurry to a processing facility, includes a tank containing the slurry, and slurry supply piping connected to the tank to allow the slurry to flow from the tank to the processing facility. A sonic wave generator is disposed along the slurry supply piping, such that sonic waves are propagated through the slurry. The sonic waves prevent the clustering of small primary abrasive particles into larger secondary abrasive particles, or break apart any clustered secondary particles, which may cause fine scratches on the surface of a wafer during a polishing operation.

Abstract: A semiconductor wafer is treated in a chamber by introducing into the chamber a silicon-containing gas or vapor and hydrogen peroxide in vapor form. The silicon-containing gas or vapor is reacted with the hydrogen peroxide to form a short chain, inorganic fluid polymer on the wafer, which thus forms a generally planar layer.

Abstract: A control signal generating circuit for generating control signals, based on a first clock signal, a second clock signal and a mode setting signal, and a plurality of scanpath circuits. Operation of each of the scanpath circuits is controlled according to the generated control signals. The control signal generating circuit and scanpath circuits are provided in a semiconductor integrated circuit having reduced size.

Abstract: There is disclosed a wiring structure for a semiconductor device being excellent in the resistance against electromigration and being able to lengthen a life of the wiring. The wiring structure is comprised of a refractory metal layer and an aluminum alloy layer being stacked on the refractory metal layer. The wiring structure contains a compound layer produced between the refractory metal layer and the aluminum alloy layer. The refractory metal layer is parted in the extended direction of the wiring to prevent the compound layer produced between the refractory metal layer and the aluminum alloy layer from being ranged in the extended direction of the wiring. A length of an interval between the parted refractory metal layer portions is set to exceed a value being twice as large as a thickness of the compound layer. This prevents the compound layer growing between faces of refractory metal layer portion being opposite to each other being ranged each other.

Abstract: A method of forming an interconnection by using a landing pad is disclosed. In a semiconductor device having a memory cell portion and a peripheral circuit portion, a refractory metal is used for the bitline instead of the usual polycide, to concurrently form a contact on an active region of an N-type and a P-type substrate. A landing pad is formed on the peripheral circuit portion at the same time as a bitline is formed on the memory cell portion. In such a process, a substantial contact hole for the interconnection is formed on the landing pad so that an aspect ratio of the contact can be lowered. Accordingly, when forming a metal interconnection, the contact hole for the interconnection is easily filled by Al-reflow so that the step coverage of the metal being deposited in the contact hole for the interconnection is enhanced, and the contact resistance is reduced. As a result, the reliability of the semiconductor device is improved.

Abstract: In the fabrication of capacitors, a TiO2 film is formed from a TiN film by means of heat-treatment within an atmosphere which does not contain oxygen. This serves to prevent the polysilicon which forms the bottom electrode from being oxidized during heat-treatment. Thus, once the bottom electrode has been formed on the silicon wafer, a TiN film and RuO2 film are formed, and the silicon wafer is heat-treated in an atmosphere which does not contain oxygen. In this manner, a dielectric film that is a TiO2 film and a top electrode that is a ruthenium film are obtained.

Abstract: A semiconductor apparatus includes a semiconductor integrated circuit including a conductive pattern; an insulating layer which is formed on the semiconductor integrated circuit to forms a plurality of base members having uneven heights; an opening which is formed through the insulating layer to expose a part of the conductive pattern; and a conductive layer which is formed on the insulating layer and the opening, the conductive layer is extending from the exposed portion of the conductive pattern to the top surface of the highest base member. An electrode is composed of the insulating layer, the opening and the conductive layer.

Abstract: A seal is formed between two parts of a high pressured chamber by means of a rigid ring (13), which is formed with curved surfaces (17), that engage with an anvil (14) and an enclosure part (10), the anvil (14) having a similar curved projection (18). At least one of the engaging surfaces is coated with a soft metal e.g. silver.

Abstract: A pre-acceleration or post-acceleration ion implantation system includes an AC (alternating current) power source supplying power in tandem with a DC (direct current) power source. The combined AC and DC power may be supplied, in alternative embodiments, to an ion accelerator and/or an ion extractor of the system.

Abstract: A power semiconductor device having an improved high breakdown voltage and improved productivity, and a fabrication method thereof are provided. The power semiconductor includes a collector region of a first conductivity type formed in a semiconductor substrate, a base region of second conductivity type formed in the collector region, and an emitter region of the first conductivity type formed in the base region. A channel stop region is formed being spaced a predetermined distance from the base region. An insulative film, a semi-insulating polycrystalline silicon (SIPOS) film, and a nitride film patterned respectively to expose the emitter region, the base region, and the channel stop region are sequentially deposited on the semiconductor substrate. A base electrode, an emitter electrode, and an equipotential electrode connected respectively to the base region, the emitter region, and the channel stop region are formed.

Abstract: The sealing resin of a semiconductor device is prevented from being peeled off from the substrate of the semiconductor device. A semiconductor device according to the present invention has a semiconductor substrate containing a central portion having a first thickness and a peripheral portion having a second thickness that is smaller than the first thickness, an electrode pad formed on the semiconductor substrate, a sealing resin for sealing the semiconductor substrate, a protruded electrode formed on the sealing resin, and a wire which electrically connects the electrode pad to the protruded electrode.

Abstract: An input terminal of an amplifier circuit is connected to a base terminal of an amplifying transistor, and is also connected to one of the terminals of capacitor via a first wiring. An output terminal of the amplifier circuit is connected to a collector terminal of the amplifying transistor, to the other terminal of the capacitor via a second wiring and also to a source voltage via a load resistor. An emitter terminal of the amplifying transistor is connected to ground via a feedback resistor. The second wiring connecting the other terminal of the capacitor and the collector terminal of the amplifying transistor is formed to intersect a cutting line, or a so-called grid line, of the wafer which is used as reference for dicing the wafer into chips.