Abstract: Sense amplifiers are respectively located at both ends of a bit line pair. These sense amplifiers amplify a voltage difference between the bit line pair in response to a sense amplifier active signal during a sensing period. Since the voltage difference between the bit line pair is amplified at the both ends of the bit line pair, the time spent amplifying the voltage between the bit line pair may be shortened.

Abstract: A method and apparatus for receiving and processing burst-mode code-division multiple access (CDMA) direct-sequence spread-spectrum (DSSS) signals is provided. In this apparatus and method, a number of demodulators are provided in a set enumerated order. Each demodulator is either “ready,” meaning that it is free to process signals, or busy meaning that it is currently processing a signal. The ready demodulators each receive an input IF signal and try to detect a preamble in the IF signal. Once they detect the preamble, each ready demodulator then sends a request signal to an arbitrator. In response to a received request signal, the arbitrator sends a grant signal to the first ready demodulator in the enumerated order. This grant signal passes through each busy demodulator that is higher in the enumerated order than the first ready demodulator. The first ready demodulator then begins processing the signal, and is moved from the set of ready demodulators to the set of busy demodulators.

Abstract: A serial access memory reduces a chip size and saves a process development.

Abstract: A quantitative and qualitative analysis of a nitrogen (N) kinetic energy peak in a spectrum of a titanium nitride (TiN) film using Auger Electron Spectroscopy (AES). The N kinetic energy peak analysis is used to set the base energy level of the AES, and is achieved by selecting a kinetic energy of an N peak which does not overlap with the Ti kinetic energy peak.

Abstract: A micro-etalon having non-beveled outer edges may be mass-produced without suffering from expected breakage problems. Such a configuration allows etalons to be mass-produced, i.e., on a wafer level. The mass-production preferably includes aligning spacer block strips to be diced with two reflective surfaces to form the etalon.

Abstract: A method of fabricating a semiconductor device is provided. In this method, a gate insulating layer and a gate are sequentially formed on a semiconductor substrate of a first conductivity type. A first active region of a second conductivity type is formed by ion-implanting a first impurity of the second conductivity type at a first dose, using the gate as a mask. Sidewall spacers are formed of an insulating material on the sidewalls of the gate. A second active region of the second conductivity type is formed by masking a narrow region between gates and ion-implanting a second impurity of the second conductivity type at a second dose higher than the first dose. Finally, a silicide layer is formed on the exposed first and second active regions and gate. There exist no impurities in excess of their solid solubility limit, which could block the diffusion of silicon in the narrow region. As a result, a reliable silicidation is ensured.

Abstract: A SOI structure semiconductor device includes a silicon substrate (1), an insulating oxide layer (2) formed on the silicon substrate (1), a SOI layer (3) formed on the insulating oxide layer (2) a LOCOS oxide layer (4) formed on the insulating oxide layer (2) and contacting with the SOI layer (3) in order to insulate the SOI layer (3), a gate insulation layer (5) formed on the SOI layer (3) and a gate electrode (6) formed on the gate insulation layer (5). The SOI layer (3) has a sectional triangle portion (10) contacting with the LOCOS oxide layer (4). The sectional triangle has an oblique side (12) as a boundary between the SOI layer (4) and the LOCOS oxide layer (3), a height side (13) equal to the thickness of the SOI layer (3) and a base on the lower boundary of the SOI layer (3), in which the ratio of the height side (13) to the base is 4:1 or less.

Abstract: A read-only memory includes a semiconductor substrate; a memory cell matrix which is formed on the semiconductor substrate; and word and bit lines which define the locations of the memory cell matrix. The memory cell matrix includes field effect transistors, each of which turns off when accessed or addressed; and conducting regions, which keep conductive state all the time. Binary data stored in the memory cell matrix are determined by detecting current flowing through the selected bit line.

Abstract: A first current cell group of an digital-to-analog converter has a first set of current cells which individually turn on and off in response to respectively input digital signals. A second current cell group of the analog-to-digital converter has a second set of current cells which respectively correspond to the first set of current cells and which individually turn on and off in response to respectively input digital signals such that an on/off state of each of the first set of current cells is opposite an on/off state of each corresponding one of the second set of current cells. The first set of currents cells are connected in parallel between a first power supply voltage and a first node, and the second set of currents cells are connected in parallel between the first node and a second power supply voltage.

Abstract: A semiconductor device includes a memory cell part which has data input terminals and which stores data received at the data input terminals and a data bus which is supplied with data. The semiconductor device also includes a transfer circuit which is coupled between the data bus and the data input terminals and which transfers the data from the data bus to the data input terminals in response to a transfer selection signal. The semiconductor device also includes a transfer control circuit which receives a bit selection signal and outputs the transfer selection signal.

Abstract: There is provided an input circuit with reduced electrical power consumption, which processes an input signal given thereto for removing the noise components contained therein and regulating the voltage level thereof as well, and then supplies an output signal therefrom to a subsequent semiconductor integrated circuit. The input circuit 101 is made up of the Schmitt buffer 111, a pull-down resistance 113, an N-transistor 115, a P-transistor 121, an N-transistor 122, a P-transistor 131, an N-transistor 132, an exclusive OR gate 141, and a bus driver 151. The Schmitt buffer 111 is a buffer which has two threshold levels i.e. upper and lower thresholds, and changes the level of the output signal OUT depending on whether the voltage of an input signal IN is higher or lower than these two threshold levels.

Abstract: A resist removing agent and a resist removing composition, having an excellent capability for removing a resist and polymer and which does not attack underlying layers, a method for preparing the same and a resist removing method using the same. The resist removing agent includes alkoxy N-hydroxyalkyl alkanamide. The resist removing composition includes alkoxy N-hydroxyalkyl alkanamide, and at least one compound selected from a group consisting of a polar material having a dipole moment of 3 or greater, an attack inhibitor and alkanolamine. A substrate having the resist thereon is brought into contact with the resist removing agent or resist removing composition to remove the resist.

Abstract: A protective layer is formed on a metallic silicide layer prior to a heat treatment for reducing a resistance of the metallic silicide layer. As a result, vertical growing of crystallization in the metallic silicide layer is restrained by the protective layer during the heat treatment. Moreover, the crystallization in the metallic silicide layer easily grows along the protective layer. Therefore, evenness of the metallic silicide layer can be maintained.

Abstract: To fill a hole or trench structure in an article, such as a semiconductor wafer, a layer is formed on the article. The layer extends over the structure so as to seal the mouth thereof. The layer may be deposited by sputtering, etc, or the layer may be deposited as a pre-formed foil. Then, the wafer and layer are subject to elevated pressure and elevated temperature such as to cause material of the layer to flow into the structure.

Abstract: A semiconductor device manufacturing apparatus, an HSG-polysilicon layer forming method, and a method for forming a capacitor having the HSG-polysilicon layer as an electrode equilibrate the temperature of a processing chamber with a temperature close to that at which a semiconductor manufacturing process occurs. The semiconductor device manufacturing apparatus includes a wafer supporter for holding a wafer during the semiconductor manufacturing process. An elevator moves the wafer supporter vertically among a load/unload position, a standby position above the load/unload position, and a process position above the load/unload position. With this apparatus, processing uniformity is enhanced.

Abstract: A method is provided for forming a multiple well of a semiconductor device is provided. By this method, a pocket well region of a first conductivity type is formed over a predetermined first region of a semiconductor substrate of a first conductivity type, using a first photolithography process. A first deep well region of a second conductivity type is then formed under the pocket well region in a self-aligned manner. A peripheral well region of the first conductivity type is selectively formed in a predetermined second region of the semiconductor substrate apart from the pocket well region, using a second photolithography process.

Abstract: An internal circuit of a semiconductor integrated circuit includes an inverter inputted with an input signal and is supplied with a power supply voltage during normal operation. The input terminal and the internal circuit are connected by a signal line having a resistor. A voltage determining circuit for determining whether a voltage of an input signal inputted to the input terminal is a signal voltage for use in the normal operation of the internal circuit or a high voltage for setting up an internal circuit test mode is connected to a node of the signal line. P-type MOS transistors are connected in series across a node of the signal line and the power supply voltage. The source of a first one of the P-type MOS transistors is connected to the power supply voltage together with the gate electrode and the substrate, and the drain is connected to the drain of the other P-type MOS transistor.

Abstract: An output unit includes a constant current source, a switching transistor that dumps the constant current when a first signal is low, and a switching transistor that outputs the constant current when a second signal is low. A drive unit includes an inverter that generates the first signal responsive to a digital signal, and an inverter that generates the second signal responsive to the digital signal inverted. Power supply terminals of the inverters are connected to an output of the current source, and the high-level voltage of the digital signal is higher than the high-level voltage at the power supply terminals. Accordingly, operation timing of the inverters is slower when changing from high level to low level, than when changing from low level to high level, so that the switching transistors do not both turn off simultaneously. This suppresses current fluctuations of the current source.

Abstract: Protective tape is bonded onto a rear surface of a semiconductor element prior to a resin sealing step, and then only a primary surface of the semiconductor element is sealed with a resin layer. Cracks and warping which would otherwise be caused by an external force or foreign matter at an exposed rear surface of the semiconductor element are prevented. This facilitates a surface polishing step and also results in a lower profile for the semiconductor device, because the rear surface is not sealed with resin.

Abstract: A rectifier circuit of a voltage genetator rectifies alternating current signals provided through electromagnetic induction of a coil. The rectified signals are boosted by rectifying the voltage of nodes of the coil by capacitors, and the voltage genetrator generates a predetermined voltage by smoothing the boosted signals using a capacitor.