Abstract: A process for fabricating a tapered trench on a silicon substrate. The process comprises the steps of forming an initial trench in the substrate and implanting nitrogen ions on the initial trench side walls. More nitrogen ions are implanted adjacent the exposed surface of the substrate than adjacent the trench bottom. Finally, the initial trench side walls are oxidized to create the tapered shape.

Abstract: An apparatus for removing material from a substrate including a plurality of polishing cells. A first polishing cell detects the material on the substrate and performs a first polishing operation for removing material from the substrate. The first polishing cell includes at least one sensor for characterizing the material on the substrate and at least one polishing tool for removing material from the substrate. A second polishing cell includes at least one polishing tool for completing the polishing process.

Abstract: A method of self-programmable Built In Self Test (BIST) for a memory (e.g., Dynamic Random Access Memory (DRAM)). The DRAM, which may be a DRAM chip, includes a DRAM core, a Microcode or Initial Command ROM, a BIST Engine, a Command Register and a Self-Program Circuit. During self test, the BIST engine may test the DRAM normally until an error is encountered. When an error is encountered, the Self-Program Circuit restarts the self test procedure at less stringent conditions. Optionally, when the DRAM tests error-free, the Self-Program Circuit may restart testing at more stringent conditions to determine DRAM functionality limits.

Abstract: A fixture for supporting a workpiece during electroplating of a metal upon the workpiece in a conductive electroplating bath includes a non-conductive frame member for receiving the workpiece therein. The fixture further includes a current distribution means having a plurality of contacts. The plurality of contacts are disposed inwardly for providing an equally distributed electrical contact with an outer perimeter region of the workpiece. The workpiece is supported between the frame member and the current distribution means. Lastly, a thief electrode is perimetrically disposed about the workpiece and spaced a prescribed distance from the workpiece by a gap region. During plating of a metal upon the workpiece, the gap region between the thief and the workpiece is filled with the conductive electroplating bath. An electroplating apparatus having a fixture for supporting a workpiece during an electroplating process and a method of supporting the workpiece to be electroplated are also disclosed.

Abstract: A method and structure for protecting a flowable oxide insulator in a semiconductor by oxidizing sidewalls of the FOX insulator, optionally nitridizing the oxidized FOX sidewalls, and then covering all surfaces of a trough or plurality of troughs in the FOX insulator, including the sidewalls, with a conductive secondary protective layer. In a multiple layer damascene structure, the surface of the FOX insulator is also oxidized, an additional oxide layer is deposited thereon, and a nitride layer deposited on the oxide layer. Then steps are repeated to obtain a comparable damascene structure. The materials can vary and each damascene layer may be either a single damascene or a dual damascene layer.

Abstract: A method of forming a shallow outdiffused buried bitline in a vertical semiconductor memory device is disclosed which utilizes annealing and oxidation to drive-in and pile-up the dopant atom into an outdiffused region. The anneal/oxidation which is carried out at two different temperature ranges allows for fabricating buried bitlines having the lowest resistance as possible at a maximum dopant concentration, yet being formed near the surface interface of the vertical pillars. Semiconductor memory devices containing the outdiffused buried bitline regions are also disclosed.

Abstract: An electrodeposition apparatus for depositing material on a surface of a substrate. The electrodeposition apparatus includes at least one contact for laterally contacting the substrate and providing electrical connection to the substrate. The at least one contact does not obscure the surface of the substrate to be plated. A voltage source is connected to the at least one contact.

Abstract: A process for making a SOI region and a bulk region in a semiconductor device. The process includes providing a SOI structure. The SOI structure has a thin silicon layer, a buried insulating oxide layer underlying the thin silicon layer, and a silicon substrate underlying the buried insulating oxide layer. Next, a nitride layer is deposited on top of the SOI structure. The SOI structure is exposed by selectively etching portions of the nitride layer. The portion of the nitride layer which is not etched forms the SOI region. The silicon substrate is exposed by selectively etching the remaining portion of the exposed SOI structure. An epitaxial layer is grown in top of the exposed silicon substrate to form the bulk region. The nitride portion above the SOI structure is finally removed.

Abstract: An apparatus for enhancing filling of structures in a substrate. At least one electrolyte evacuator adjacent a surface of a substrate including the structures evacuates electrolyte from the structures. At least one electrolyte injector adjacent the surface of the substrate including the structures injects electrolyte into the structures.

Abstract: A process for making a capacitor for a silicon-on-insulator (SOI) structure. The SOI structure has a p-type silicon base layer, a buried oxide layer, a silicon layer, and an n+ layer formed within a portion of the p-type silicon base layer. The process comprises the steps of forming a buried oxide layer and a silicon layer in the p-type silicon base layer, forming an n+ layer in a portion of the p-type silicon base layer, and forming electrically conductive paths to the p-type silicon base layer and the n+ layer extending through the buried oxide and silicon layers.

Abstract: An integrated circuit (IC) chip wherein a built-in self test determines the IC's optimum electrical performance. A corresponding optimum performance setting is stored in NVRAM on the chip. Upon each chip power-up, the optimum performance setting is retrieved and provided to chip control which sets the chip for its best performance.

Abstract: A planar silicon-on-insulator (SOI) structure and a process for fabricating the structure. The SOI structure has a silicon wafer, an oxide layer, and a silicon layer. Trenches are formed, extending from the top surface of the structure to the silicon wafer, and are filled with a semiconductor. The trenches have a top, a bottom, and side walls. The side walls have side-wall silicon portions. The side-wall silicon portions of the trench side walls are covered by trench side-wall oxide layers. A protective side wall extends over the trench side walls and trench side-wall oxide layers from the trench top to the trench bottom.

Abstract: A semiconductor memory device including at least three of the following cell structures: an NVRAM cell structure, an FERAM cell structure, a DRAM cell structure, and an SRAM cell structure. The cell structures are disposed on the same substrate and preferably have gate surfaces which are substantially coplanar. An NVRAM cell structure. Processes for forming a memory structure that includes NVRAM, FERAM, DRAM, and/or SRAM memory structures on one substrate and processes for forming a new NVRAM cell structure.

Abstract: A method of forming a semiconductor structure having features of differing sizes, includes forming a first layer on a semiconductor substrate; patterning only a first plurality of features of a first feature size on the first layer; removing portions of the first layer, the portions corresponding to the first plurality of features, filling the first plurality of openings; forming a second layer, the second layer overlying the first layer and the filled openings; patterning a second plurality of features of a second feature size on the second layer; removing portions of the first layer and second layer, the portions corresponding to the second plurality of features, the second plurality of openings extending through the first and second layers, and filling the second plurality openings.

Abstract: An anode assembly includes a perforated anode and an electrical contact assembly attached to the anode. A perforated anode holder holds the anode. The anode holder includes perforations at least in a bottom wall such that plating solution may flow through perforations in the anode holder and perforations in the anode. An anode isolator separates the anode and a cathode. The anode isolator includes at least one curvilinear surface. The contact assembly includes a closed or substantially closed cylinder member of titanium or titanium alloy, a copper lining or disk disposed within the cylinder, and a titanium or titanium alloy post fixed and in electrical engagement with the lining or disk.

Abstract: The present invention provides an apparatus for setting the free-running frequency of a VCO to a reference frequency. The apparatus comprises frequency range means for setting the VCO within a VCO frequency range among a plurality of VCO frequency ranges. First counting means are operable to count to a first value at the VCO frequency rate and to provide a first ending signal when the first value is reached. Second counting means are operable to count to a second value at the reference frequency rate and to provide a second ending signal when the second value is reached. The second counting means are also operable to provide a reference count value when the first value is reached by the first counting means. A state machine is responsive to the first and second counting means for selecting a VCO frequency range among the plurality of VCO frequency ranges such that the VCO free-running frequency obtained through the selected range gives the closest value to the reference frequency.

Abstract: A method for fabricating an integrated circuit package or arrangement includes providing a carrier having a surface topography of projections or recesses for supporting individual semiconductor circuit chips having conversely matching bottom surface topographies to permit self-aligned positioning of the chip on the carrier. Chips are provided such that top faces of neighboring chips lie substantially in planes separated by a distance of greater than 0.0 .mu.m. The carrier is arranged and dimensioned such that the neighboring chips are separated by a gap G or spacing in a range of 1 .mu.m<G.ltoreq.100 .mu.m. A metallic interconnect is provided over the top faces and the gap. Preferably, the interconnect has a gradual slope over the gap.

Abstract: A fixture for supporting a workpiece during electroplating of a metal upon the workpiece in a conductive electroplating bath includes a non-conductive frame member for receiving the workpiece therein. The fixture further includes a current distribution means having a plurality of contacts. The plurality of contacts is disposed inwardly for providing an equally distributed electrical contact with an outer perimeter region of the workpiece. The workpiece is supported between the frame member and the current distribution means. Lastly, a thief electrode is perimetrically disposed about the workpiece and spaced a prescribed distance from the workpiece by a gap region. During plating of a metal upon the workpiece, the gap region between the thief and the workpiece is filled with the conductive electroplating bath. An electroplating apparatus having a fixture for supporting a workpiece during an electroplating process and a method of supporting the workpiece to be electroplated are also disclosed.

Abstract: An integrated circuit package or arrangement includes a carrier having a surface topography of projections or recesses for supporting individual semiconductor circuit chips having conversely matching bottom surface topographies to permit self-aligned positioning of the chips on the carrier. Top faces of neighboring chips lie substantially in planes separated by a distance of greater than 0.0 .mu.m. The neighboring chips are separated by a gap G or spacing in a range of approximately 1 .mu.m<G.ltoreq.approximately 100 .mu.m. A metallic interconnect is disposed over the top faces and the gap. Preferably, the interconnect has a gradual slope over the gap.

Abstract: A planarizing method involves a first polishing step in which a relatively hard, low compressibility pad removes excess material of a first layer and planarizes the first layer. Deep defects emanating from the polishing surface formed during the first polishing step are then enlarged and filled with a second layer. After filling, and optionally annealing, the second layer is planarized by polishing with a relatively soft and high compressibility pad or by anisotropic etching.