Abstract: A dynamic random access memory device formed in a substrate having a trench. The trench has a side wall, a top, a lower portion, and a circumference. The device includes a signal storage node including a metallic storage node conductor formed in the lower portion of the trench and isolated from the side wall by a node dielectric and a collar oxide above the node dielectric. Preferably, the trench has an aspect ratio of greater than 50. A buried strap is coupled to the storage node conductor and contacts a portion of the side wall of the trench above the collar oxide. A trench-top dielectric which is formed upon the buried strap has a trench-top dielectric thickness.

Abstract: A method and system for optimizing the execution of a collection of related modules by eliminating redundant modules from the collection. The collection of modules represent a set of related simulation experiments and are organized as generations of related module sequences having execution interdependencies. The method eliminates redundant modules in the collection by redefining execution interdependencies among the modules. Groups of equivalent modules are formed by comparing the modules within each generation to each other to determine which modules are equivalent. Modules having equivalent execution prerequisites and which will produce the same output given the same input are considered equivalent. In each group of equivalent modules, a single “target” module is selected to substitute for the others in the module execution sequences, and execution interdependencies are redefined to effect the substitution.

Abstract: A solid-state CCD device suitable for forming into arrays and for use with suitable hardware to form video image capture devices and methods for fabricating same are provided.

Abstract: A silicon-germanium base capable of use in heterojunction bipolar transistor includes a silicon substrate having a mesa surrounded by a trench. The mesa has a top surface and a silicon-germanium layer is disposed only on the top surface of the mesa. In addition, a heterojunction bipolar transistor includes the silicon-germanium base as described.

Abstract: A barrier film for a semiconductor device structure. The barrier film includes a compound including nitrogen and at least one of titanium or tantalum, nitrogen in a concentration that varies within the barrier film, and oxygen in a concentration that varies within the barrier film.

Abstract: A bandgap reference voltage circuit having a bandgap start-up circuit for initiating operation of the bandgap reference voltage circuit, a bandgap core circuit for developing a bandgap reference voltage, and a bandgap output circuit for supplying a bandgap reference voltage. The bandgap start-up circuit is connected to a low impedance leg in the bandgap core circuit and the bandgap output circuit has a feedback circuit that is connected to a high impedance leg in the bandgap core circuit. The connection of the bandgap start-up circuit to the low impedance leg of the bandgap core circuit eliminates the possibility of metastable operation of the bandgap reference voltage circuit. This bandgap reference voltage circuit can be used in battery powered units having reduced supply voltages as low as, for example, 1.7V and the arrangement of the feedback circuit of the bandgap output circuit allows supplying of reference voltages greater and less than typical bandgap voltage.

Abstract: An SOI chip having an isolation barrier. The SOI chip includes a substrate, an oxide layer deposited on the substrate, and a silicon layer deposited on the oxide layer. A gate is deposited above the silicon layer. A first metal contact is deposited above the gate to form an electrical contact with the gate. Second and third metal contacts are deposited to form electrical contacts with the silicon layer. The isolation barrier extends through the silicon layer and the oxide layer, and partially into the substrate, to block impurities in the oxide layer outside the isolation barrier from diffusing into the oxide layer inside the isolation barrier. The isolation barrier surrounds the gate, the first metal contact, the second metal contact, and the third metal contact—which define an active chip area inside the isolation barrier. A method of manufacturing the SOI chip is also disclosed.

Abstract: The magnetic field of an inductor is decreased by the presence of one or more single loop windings positioned in proximity to the inductor. The single loop windings have open circuits that are selectively closed to magnetically couple the single loop windings to the inductor. A switched inductor/varactor tuning circuit is formed by connecting a varactor to the inductor.

Abstract: In a very dense integrated circuit package, including a carrier having a topography of projections with sloping sides for supporting individual semiconductor circuit chips with a conversely matching bottom surface topography to permit self-aligned positioning of the chip on the carrier, a method for compensating for variations in chip thickness by controlling the width of recesses in bottom surface topography so that alignment on the carrier projections will elevate thinner chips so that the device side of the chips are co-planar.

Abstract: A method for forming a JOI structure which allows for reduction in both source/drain junction leakage and capacitance is provided. In the inventive method, an insulator layer is formed under the source/drain regions, but not under the channel region. The insulator layer is formed in the present invention after forming the gate stack region and recessing the semiconductor surface surrounding the gate stack region, followed by deposition of a conductive material such as polysilicon and, optionally, heavy source/drain diffusion formation.

Abstract: A 2F2 flash memory cell structure and a method of fabricating the same are provided. The 2F2 flash memory cell structure includes a Si-containing substrate having a plurality of trenches formed therein. Each trench has sidewalls that extend to a bottom wall, a length and individual segments that include two memory cell elements per segment. Each memory cell element comprises (i) a floating gate region having L-shaped gates formed on a portion of each trench sidewall; (ii) a program line overlapping one side of the L-shaped gates present at the bottom wall of each trench and extending along the entire length of the plurality of trenches; and (iii) a control gate region overlying the floating gate region. The control gate region includes gates formed on portions of the sidewalls of the trenches that are coupled to the floating gate regions.

Abstract: A 6F2 memory cell structure and a method of fabricating the same. The memory cell structure includes a plurality of memory cells located in a Si-containing substrate which are arranged in rows and columns. Each memory cell includes a double-gated vertical MOSFET having exposed gate conductor regions and two gates formed on opposing sidewalls of the MOSFETs. The memory cell structure also includes a plurality of wordlines overlaying the double-gated vertical MOSFETs and in contact with the exposed gate conductor regions, and a plurality of bitlines that are orthogonal to the wordlines. Trench isolation regions are located adjacent to the rows of memory cells. The memory cell structure also includes a plurality of punch through stop regions located in the Si-containing substrate and self-aligned to the wordlines and bitlines. A portion of the punch through stop regions overlap each other under the bitlines and each region serves to electrically isolate adjacent buried-strap regions from each other.

Abstract: A gate-controlled device includes an inverted-T gate which overlaps lightly doped, shallow extension regions formed in an underlying base layer. Spacers are included on the sides of the gate, and source/drain regions are formed in the base layer in non-overlapping relationship with the gate layer. This device outperforms conventional devices in terms of performance. Lower external resistance is achieved by forming a gate-controlled inversion channel over at least a portion of the shallow LDD extensions, and by making the shallow LDD extensions graded (or sloped) towards the deep source/drain regions. Also, forming portions of the gate underneath the spacers, electrical gate control of the shallow LDD junctions is made possible. This advantageously reduces the series resistance of the device and increases drive current, both of which translate into improved device performance with no increase in gate-to-source/drain parasitic capacitance.

Abstract: A JOI structure and cell layout including at least one patterned gate stack region present atop a semiconductor substrate, said semiconductor substrate having source/drain diffusion regions of opposite dopant polarity abutting each other present therein, said source/drain diffusion regions are present atop an insulating layer, said insulating layer not being present beneath said at least one patterned gate stack region.

Abstract: An integrated circuit, comprising: a semiconductor substrate, a plurality of last metal conductors disposed above said substrate, a bottom metallic layer disposed on said last metal conductors, a top metallic layer, and an alpha absorber disposed between said bottom and top metallic layers, said alpha absorber consisting essentially of a high-purity metal which is an alpha-particle absorber. The metal is, for example, of Ta, W, Re, Os or Ir.

Abstract: Candidate locations in which each of the components is to be placed are assumed. Initially, all the cells on a printed circuit board are the candidates. The range of candidates for the location of each component is narrowed down in some way (for example, the farthest cell from a fixed component is excluded from candidates for the location in which a component that directly relates to the fixed component is to be placed). An approximation problem is created from an original placement problem and a solution that optimizes the approximation problem is find. This solution is a feasible solution of the original placement problem as well. The process of narrowing down the candidates and solving the approximation problem is repeated until one candidate (or more than one candidate having an equal evaluation value) is found ultimately to determine the placement of the component.

Abstract: To overcome problems in an image reject mixer in a radio frequency receiver when there is a degradation in image rejection due to process variations, such as variations in the values of components, a reactance feedback path of a first differential amplifier in the intermediate frequency combiner of the image reject mixer is tuned during assembly of the radio frequency receiver. This tuning places the first differential amplifier and a second differential amplifier in the intermediate frequency combiner in phase quadrature when the pole frequency of reactance feedback path is at least ten times lower than the frequency of the intermediate frequency and sets the gain of the two differential amplifiers to be equal when the reactance of the reactance feed back path in the first differential amplifier is equal to the resistance of a resistance feedback path in second differential amplifier.

Abstract: Apparatus and method for reducing clock skew. A compensator is connected to receive an uncorrected clock signal and delay the clock signal in accordance with a skew control voltage. The skew control voltage is derived from the signal to noise ratio of an analog signal produced by a device controlled by the clock signal. The skew control voltage changes step wise maintaining the system signal to noise at a minimum by reducing the clock skew.

Abstract: A method for forming a substrate contact in a substrate that includes a silicon on insulator region. A shallow isolation trench is formed in the silicon on insulator substrate. The shallow isolation trench is filled. Photoresist is deposited on the substrate. A contact trench is formed in the substrate through the filled shallow isolation trench, silicon on insulator, and silicon substrate underlying the silicon on insulator region. The contact trench is filled, wherein the material filling the contact trench forms a contact to the silicon substrate.

Abstract: Increased pixel density and increased sensitivity to blue light are provided in a charge couple device employing sidewall and surface gates.