Abstract: An integrated circuit package having a carrier and semiconductor circuit chips are disclosed. The carrier has a topography of mesas projected from its surface. Each of the semiconductor circuit chips has a device side surface and an opposite bottom surface, which has a topography of a recess conversely matching a respective one of the mesas of the carrier for self-alignment positioning on the carrier. To offset the variation in the thickness of the semiconductor circuit chips, the width of the recess in each semiconductor circuit chip is controlled so that the alignment of the recess on its respective mesa elevates the bottom surface of the semiconductor circuit chip. Therefore, the device side surfaces of the semi conductor circuit chips are placed in the same plane.

Abstract: Resist developers can attack some advanced dielectric materials such as silsesquioxane materials which can be used as an insulator between a surface of an integrated circuit chip and wiring layers formed on the surface of the dielectric material. By performing a resist stripping or etching process in which a reactant material is supplied externally or liberated from the dielectric material, an extremely thin surface protective covering of an intermediate material may be formed which is impervious to resist developers or any of a plurality of other materials which may damage the flowable oxide material. A dual Damascene process for forming robust connections and vias to the chip can thus be made compatible with advanced dielectrics having particularly low dielectric constants to minimize conductor capacitance and support fast signal propagation and noise immunity even where conductors are closely spaced to each other.

Abstract: A voltage regulator that establishes a bandgap voltage reference and achieves output voltage regulation with a single feedback loop. The bandgap voltage reference is established by equal current flow through each of two branches of a proportional to absolute temperature current mirror. The equal current flow through the two branches of the proportional to absolute temperature current mirror is achieved by the feedback loop controlling the current flow in response to the bandgap voltage reference. This same feedback loop, responsible for establishing the bandgap voltage, also establishes the regulated output voltage through a pass transistor by means of maintaining a fixed voltage ratio between the bandgap voltage and the regulated output voltage through a resistor string.

Abstract: A SOI field effect transistor structure providing ESD protection. The structure has a source, a drain, a body, and a gate. The gate is formed from a thick oxide layer and a metal contact. The gate is formed during the BEOL process. The transistor may be a p-type transistor or an n-type transistor. The transistor may have its drain tied to either the gate, the body, or both the gate and body. When used as a protection device, the drain is tied to a signal pad and the source is tied to a potential reference.

Abstract: The present invention relates generally to a CVD (Chemical Vapor Deposition) process where at least one source metal, such as, nickel (Ni) or alloys thereof, for example, Ni/Cu, Ni/Co, are deposited on metal surfaces which are capable of receiving the source metal, such as, refractory metal, for example, molybdenum, tungsten or alloys thereof, using at least one gaseous Iodide source, such as, an iodic fluid, for example, hydriodic acid gas. The source metal is securely held in place by at least one high strength inert material.

Abstract: A method for plating a second metal directly to a first metal without utilizing a mask. A semiconductor substrate is provided including at least one metal feature and at least one insulating layer covering the metal feature and the substrate. At least one recess is formed in the at least one insulating layer thereby exposing at least a portion of the metal feature. At least one conductive barrier layer is formed over the insulating layer and the exposed portion of the metal feature. A plating seed layer of a first metal is formed over the at least one barrier layer. A photoresist layer is deposited over the plating seed layer. Portions of the photoresist layer and portions of the plating seed layer outside of the at least one recess are removed. Photoresist remaining in the at least one recess is removed. A second metal is electroplated to the plating seed layer in the recess, using the barrier layer to conduct electrical current.

Abstract: A multistack 3-D semiconductor structure comprising a first level structure comprising a first semiconductor substrate and first active devices; and a second level structure comprising a SOI semiconductor structure bonded to the first level structure and further comprising second active devices; and wherein the first active devices are more heat tolerant than the second active devices is provided along with a method for its fabrication.

Abstract: A radio frequency power amplifier for a battery powered handset unit of a wireless communications system having a low power signal amplification path and a high power signal amplification path. Logic and biasing means within the handset select between the low power signal path and the high power signal depending upon the handset being within or outside a prescribed distance from a base station. In this way, the signals received at the base station from the handset are at the required power level.

Abstract: An SOI chip having an isolation barrier. The SOI chip includes a substrate, an oxide layer deposited on the substrate, and a silicon layer deposited on the oxide layer. A gate is deposited above the silicon layer. A first metal contact is deposited above the gate to form an electrical contact with the gate. Second and third metal contacts are deposited to form electrical contacts with the silicon layer. The isolation barrier extends through the silicon layer and the oxide layer, and partially into the substrate, to block impurities in the oxide layer outside the isolation barrier from diffusing into the oxide layer inside the isolation barrier. The isolation barrier surrounds the gate, the first metal contact, the second metal contact, and the third metal contact—which define an active chip area inside the isolation barrier. A method of manufacturing the SOI chip is also disclosed.

Abstract: A method for forming source/drain extensions with gate overlap. An oxide layer is formed on a semiconductor substrate and a gate structure on the semiconductor substrate. First, sidewall spacer regions are formed on sides of the gate structure. Second spacer regions are formed on sides of the sidewall spacer regions. Upper regions of the gate structure and the sidewall spacer regions are silicided. Portions of source and drain extension regions in the semiconductor substrate adjacent the gate structure are also silicided.

Abstract: Poorly adherent layers such as silicon nitride and silicon dioxide exhibit improved adhesion to copper member by providing an intervening germanium-containing layer. The germanium-containing layer is copper germanide, germanium oxide, germanium bitride or combinations thereof. The germanium-containing layer enhances the adhesion such that the poorly adherent layer is less susceptible to delamination from the copper member.

Abstract: The present invention relates generally to high density pluggable connector array and process thereof. More particularly, the invention encompasses a structure comprising high density pluggable connector arrays. A process for making such types of high density pluggable connector arrays is also disclosed.

Abstract: A semiconductor device is fabricated by implanting into a semiconductor substrate non-doping ions at a tilt angle of at least about 10° to laterally extend preamorphization of the substrate portion and then implanting into the substrate dopants for providing source/drain extensions or halo doping or both.

Abstract: An apparatus and method for an electrodeposition or electroetching system. A thin metal film is deposited or etched by electrical current through an electrolytic bath flowing toward and in contact with a target on which the film is disposed. Uniformity of deposition or etching is promoted, particularly at the edge of the target film, by baffle and shield members through which the bath passes as it flows toward the target. The baffle has a plurality of openings disposed to control the localized current flow across the cross section of the workpiece/wafer. Disposed near the edge of the target, the shield member shapes the potential field and the current line so that it is uniform.

Abstract: A process for creating a substrate including bulk silicon regions and semiconductor-on-insulator regions. Regions of a surface of a bulk silicon substrate are recessed above regions where it is desired to create buried oxide regions in the substrate. Implant mask regions are formed on the surface of the substrate over regions where it is not desired to create buried oxide regions. Buried oxide regions are formed in the substrate under the recessed regions in the substrate. The implant mask regions are removed, leaving bulk silicon regions between the buried oxide regions.

Abstract: A process for plating metal in submicron structures. A seedlayer is deposited on surfaces of submicron structures. The seedlayer is annealed at a temperature of about 80° C. to about 130° C. Metal is plated on the seedlayer.

Abstract: A homogeneous marker is formed, possibly by the adsorption of trace amounts of an ambient material such as carbon monoxide gas, at a surface of a deposited material when the plasma in momentarily interrupted during plasma enhanced chemical vapor deposition or other deposition processes involving the presence of a plasma. When the deposited material is etched, the resulting crystal dislocations or adsorbed gas is detected as a marker by optical emission spectroscopy techniques. The accuracy of an end point determination of the etching process can be increased by providing a sequence of such markers within the bulk or volume of the deposited material. The markers, being merely an interface such as a slight crystal dislocation in otherwise homogeneous material, do not affect the electrical, chemical or optical properties of the remainder of the predetermined deposited material and thus the homogeneity of the deposited material is not significantly affected.

Abstract: A semiconductor memory device including at least three different types of memory cell structures. The types include an NVRAM cell structure, an FERAM cell structure, a DRAM cell structure, and an SRAM cell structure. The cell structures are disposed on the same substrate.

Abstract: A process for forming a planar silicon-on-insulator (SOI) substrate comprising a patterned SOI region and a bulk region, wherein the substrate is free of transitional defects. The process comprises removing the transitional defects by creating a self-aligned trench adjacent the SOI region between the SOI region and the bulk region.

Abstract: A field effect transistor which comprises a semiconductor substrate having a source region and a drain region separated by a channel region; a conductive floating gate formed over a first portion of the channel region adjacent to the doped source region and recessed into the semiconductor substrate; and being separated from the first portion of the channel region by a first insulation layer; and a conductive control gate formed substantially over but electrically isolated from the floating gate and formed over the entire channel region; along with a method for fabricating such is provided.