Abstract: A mixer for a wireless communications system having a differential amplifier that translates an input intermediate frequency voltage signal or an input radio frequency voltage signal to current signals that are supplied to a doubly-balanced switching modulator that develops a differential mixed output radio frequency signal or intermediate frequency signal that is the product of the current signals and a local oscillator signal. Included in the differential amplifier are a first reactance circuit and a second reactance circuit each of which provides a low impedance to ground at the second harmonic of the local oscillator signal and a high impedance at the frequency of the input radio frequency signal or input intermediate frequency signal.

Abstract: A compact BALUN transformer comprises a primary and a secondary conductor loop. Each of these loops are disposed in a substantially flat spiral configuration. However, one of these loops, either the primary or the secondary, is preferably disposed in a multi-layer (stacked) configuration. The stacking of at least one of the primary or secondary layers in a multi-layer arrangement provides an increase of impedance in one of the loops. This increased impedance for impedance matching purposes comes with the advantage that parasitic capacitance between primary and secondary layers as would normally be introduced in a multi-layer configuration is absent. In another embodiment of the present invention, both conductor loops are disposed in a multi-layer configuration. Such configurations are particularly useful for 1 to 1 impedance matching conditions and for somewhat lower frequency BALUN circuits.

Abstract: A balun transformer having two series connected transformers with each having a primary loop conductor disposed in a stacked configuration. One portion of each primary loop conductors is in a first layer and these two portions of the two primary loop conductors are connected in series. The second portions of the primary loop conductors are in a second layer that is spaced from the first layer with the secondary loop conductors interlaced with these portions of the primary loop conductors in the second layer.

Abstract: By sampling at six times the carrier frequency cosine and sine multiplication circuits are found to be constructable from simple shift and inversion circuit. Shifting and inversion are controlled by means of a simple finite state machine or other circuits cycling through a six cycle periodic sequence.

Abstract: A process for removing material from a substrate. The material is exposed to an aqueous solution comprising about 4% to about 30% of at least one acid and at least one surfactant.

Abstract: A bias network for a radio frequency signal power amplifier. A current source is connected to a source of band gap voltage and produces a current proportional to the voltage. A reference voltage circuit receives the current and produces a voltage which is proportional to the current, as well as changes in temperature. An operational amplifier is used to connect the reference voltage to the power amplifier, so that the power amplifier is effectively isolated from the reference voltage circuit and current bearer circuit. A power amplifier breakdown protection circuit is connected across the output of the operational amplifier for diverting avalanche current produced form the power amplifier away from the power amplifier when the power amplifier output is mismatched through the antenna. Baseband signal transmission from the power amplifier to the bias network circuit is also significantly reduced, thus avoiding the generation of spurious radiation components.

Abstract: A multi-chip module and heat-sink cap assembly and method of fabrication, which provides sufficient cooling for higher power density chips. The heat-sink cap has heat-sink columns disposed over each chip on a substrate. The heat-sink columns are interconnected by flexible members to provide a unitary cover. Thin film metallization of at least a portion of the mating surfaces of the substrate, chips and heat-sink column permits soldering of the cap to the chips and substrate to form the package which is a mechanically stable structure with no degradation of interconnection fatigue life due to thermal cycling of the assembly when in use.

Abstract: A method is described for electroplating a metal structure in a feature formed in a substrate. A seed layer of the metal is deposited on the top surface and on the bottom and sidewalls of the feature. The seed layer is then selectively removed from the top surface, so that only a portion of the seed layer remains in the feature on at least the bottom thereof. The metal is then electroplated using this portion of the seed layer, so that the metal fills the feature. The removal of the seed layer from the top surface causes no electroplating to occur on the top surface.

Abstract: A p-type MOSFET having very shallow p-junction extensions. The semiconductor device is produced on a substrate by creating a layer of implanted nitrogen ions extending from the substrate surface to a predetermined depth preferably less than about 800 Å. The gate electrode serves as a mask so that the nitrogen implantation does not filly extend under the gate electrode. Boron is also implanted to an extent and depth comparable to the nitrogen implantation thereby forming very shallow p-junction extensions that remain confined substantially within the nitrogen layer even after thermal treatment. There is thus produced a pMOSFET having very shallow p-junction extensions in a containment layer of nitrogen and boron in the semiconductor material.

Abstract: A semiconductor device structure including a substrate including at least one silicon-on-insulator substrate region and at least one non-silicon-on-insulator region. The at least one silicon-on-insulator region and at least one non-silicon-on-insulator region are formed in a pattern in the substrate. At least one trench is arranged in the vicinity of at least at a portion of a boundary between a silicon-on-insulator substrate region and the non-silicon-on-insulator substrate region. The at least one trench is arranged in at least one of the silicon-on-insulator region and the non-silicon-on-insulator region.

Abstract: Resist developers can attack some advanced dielectric materials such as silsesquioxane materials which can be used as an insulator between a surface of an integrated circuit chip and wiring layers formed on the surface of the dielectric material. A first protective layer is formed in situ on the dielectric material, such as by exposing the material to an oxygen-containing or flourine containing plasma. Also, by performing a resist stripping or etching process in which a reactant material is supplied externally or liberated from the dielectric material, an extremely thin surface protective covering of an intermediate material may be formed which is impervious to resist developers or any of a plurality of other materials which may damage the flowable oxide material. The first protective layer and the surface protective covering can be formed by essentially identical processes.

Abstract: A multipurpose current source for generating a current with linear positive temperature dependence at a predetermined slope. This multipurpose current source includes a proportional to absolute temperature (PTAT) current source, a constant current generation circuit coupled to the PTAT current source circuit and a circuit coupled to the PTAT current source circuit and the constant current generation circuit by which a temperature dependent current developed by the PTAT current source and a constant current independent of temperature developed by the constant current generation circuit are combined The linear positive temperature dependent current is generated by subtracting to develop a temperature dependent current by reducing the temperature dependent current developed by the PTAT current source by the constant current independent of temperature developed by the constant current generation circuit.

Abstract: An amplifier in which the gain is changed by changing the reactance in the emitter of a transistor and this change in reactance is compensated for by changing the reactance in a feedback path between the collector and the base of the transistor to maintain the input impedance to the amplifier fixed.

Abstract: An alpha-phase tantalum having a resistivity of about 15 micro-ohm-cm or less is provided and is especially useful as a barrier layer for copper and copper alloy interconnections.

Abstract: An apparatus for testing structures in semiconductor wafers. The apparatus includes at least one test probe. At least one tool measures and controls deceleration of the at least one test probe as it approaches a surface of a structure in the semiconductor wafer.

Abstract: A barrier film for a semiconductor device structure. The barrier film includes a compound including nitrogen and at least one of titanium or tantalum, nitrogen in a concentration that varies within the barrier film, and oxygen in a concentration that varies within the barrier film.

Abstract: A process for making a capacitor for a silicon-on-insulator (SOI) structure. The SOI structure has a p-type silicon base layer, a buried oxide layer, a silicon layer, and an n+ layer formed within a portion of the p-type silicon base layer. The process comprises the steps of forming a buried oxide layer and a silicon layer in the p-type silicon base layer, forming an n+ layer in a portion of the p-type silicon base layer, and forming electrically conductive paths to the p-type silicon base layer and the n+ layer extending through the buried oxide and silicon layers.

Abstract: The present invention provides a method for forming dual workfunction metal oxide semiconductor field effect transistors (MOSFETs) which utilizes processing steps that solve the problem of doping the dual work function MOSFETs, while providing contacts to the diffusion regions which are borderless to the gate conductors. Specifically, the present invention provides a method wherein a self-aligned insulating gate cap is formed on top of a previously defined and doped gate conductor region. The inventive method which forms an insulating cap that is self-aligned to an underlying gate conductor enables the formation of dual workfunction gate conductors and borderless diffusion contacts without the need of employing separate block masks as required by prior art processes.

Abstract: A semiconductor structure having silicon dioxide layers of different thicknesses is fabricated by forming a sacrificial silicon dioxide layer on the surface of a substrate; implanting nitrogen ions through the sacrificial silicon dioxide layer into first areas of the semiconductor substrate; implanting chlorine and/or bromine ions through the sacrificial silicon dioxide layer into second areas of the semiconductor substrate where silicon dioxide having the highest thickness is to be formed; removing the sacrificial silicon dioxide layer; and then growing a layer of silicon dioxide on the surface of the semiconductor substrate. The growth rate of the silicon dioxide will be faster in the areas containing the chlorine and/or bromine ions and therefore the silicon dioxide layer will be thicker in those regions as compared to the silicon dioxide layer in the regions not containing the chlorine and/or bromine ions.

Abstract: Method and structures for making a highly reliable metal interlock structure with continuous via and line structures. The absence of barrier layers between vias and lines or absence of interlevel dielectric layer is used to enhance chip performance.