Abstract: A method for planarizing a layer (18) begins by forming a layer (18) over a wafer having a substrate (12). Layer (18) has a surface topography which is not planar. A layer of material (20) is formed over the layer (18). The layer of material (20) has a surface which is more planar than the surface of layer (18). The surface of material (20) is transferred into the layer (18) by etching the layer (18) and the material (20) at approximately the same etch rate. The same etch rate is achieved by monitoring one of either the surface of the wafer or the etch environment of an etch system chamber. A computer-controlled feedback path alters an etch chemistry or etch environment to maintain the etch rates within an etch rate tolerance which is also referred to as a process window. By monitoring and altering the etch environment and/or the etch chemistry to maintain a process window, an optimal planar surface is achieved for layer (18).

Abstract: A zero detection method (FIG. 5) and a zero detection apparatus (FIGS. 2-4) involves determining if the sum of at least two operands and a carry-in bit will produce a zero result. The zero detection is performed in parallel to another system calculation, such as an addition or subtraction of the two operands. The zero detection logic has a hierarchical structure (see FIG. 4) which is used to reduce logic and quicken the zero detect process of FIG. 5. Zero detection may occur for more than one group of bits within the two operands. The zero detection is used, in a preferred form, primarily in floating point operations such as floating point additions.

Abstract: A process for forming a transistor (10) begins by providing a substrate (12). Field oxide regions (14) or equivalent isolation is formed overlying or within the substrate (12). A gate oxide (16) and a conductive layer (18) are formed. A masking layer (20) is formed overlying the conductive layer (18). The masking layer (20) and the conductive layer (18) are etched to form a gate electrode and define a drain region (19) and a source region (21). Spacers (22) are formed adjacent the gate electrode. First silicided regions (26) are formed over the source and drain regions (21 and 19 respectively). The masking layer prevents the gate electrode from siliciding. The masking layer (20) is removed and a second silicided region (30) is formed overlying the gate electrode. The second silicided region (30) and the silicided regions (26) are made of different silicides.

Abstract: A data processing system (90) having a serial scan circuit (10). The serial scan circuit (10) has an address detector (12) for detecting and decoding M serially-provided address bits. Coupled to the address detector (12) is a clock generator (14) which is used for providing at least one derived clock signal. Coupled to the address detector (12) and the clock generator (14) is a serial scan chain (16) which is used to store N serially-provided data bits. A plurality of serial scan chains (10) is connected in a parallel configuration and used to form the data processing system (90). The M address bits and the N data bits are serially provided via a single conductor (24) in a time division multiplexed operation. Integrated circuit surface area is reduced by avoiding large address and data buses, and bus routing.

Abstract: A shielding structure (10) and method of formation. The shielding structure (10) has a substrate (12). A first dielectric layer (14) overlies the substrate (12). A conductive layer (16) is formed overlying the dielectric layer (14), is patterned, and is etched to form electrically isolated conductive regions from conductive layer (16). The electrically isolated conductive regions have sidewalls and the etching of conductive layer (16) exposes portions of dielectric layer (14). The exposed portions of dielectric layer (14) are etched to form trenched portions of dielectric layer (14). A second dielectric layer (18) is formed overlying the electrically isolated conductive regions, including the sidewalls, and overlying the trenched portions to create recessed regions that separate the electrically isolated conductive regions.

Abstract: A vertically raised transistor (10) is formed having a substrate (12). A conductive plug region (22) is selectively or epitaxially formed to vertically elevate the transistor (10). A first doped region (16a) and a second doped region (16b) are each electrically coupled to the conductive plug region (22) via sidewall contacts. The doped regions (16a and 16b) are used to form current electrode regions (26) within the conductive plug region (22). A channel region separates the current electrodes (26). A gate dielectric layer (28) is formed to overlie the channel region. A conductive layer (30) is formed to overlie the gate dielectric layer (28). Conductive layer (30) forms a gate electrode for the transistor (10). The vertical raised transistor (10) and conductive plug region (22) provide improved device isolation and improved device operation.

Abstract: A method for processing exception conditions in a floating-point system (40) begins by determining in hardware that an exception will occur (14) for a given floating-point operation and operand(s). After the hardware determines that an exception is to occur, an exception handler is invoked from software. The exception handler numerically alters the operands to create biased operands which may be processed by the hardware (20) via the given floating-point operation without creating another exception condition. The biased operands are then processed by the hardware via the given floating-point operation to produce a biased floating-point result. The biased floating-point result is unbiased (22) by the exception handler to achieve an unbiased result. The speed of floating-point exception handling is improved by using biasing techniques and both software and hardware to mathematically resolve floating-point exceptions to correct unbiased results.

Abstract: A method and apparatus for detecting and completing floating point operations involving special floating point operands is performed in parallel, via a circuit (24), to the operation of at least one floating point mathematical unit (18, 20or 22). The floating point control (30) along with registers (14 and 16) provide floating point operands and floating point control to the mathematical units (18, 20, and 22). If the mathematical units (18, 20, and 22) cannot perform a proper floating point calculation because of the presence of a special operand, then the circuit (24) will detect the special operand and complete the floating point operation in a proper manner by communicating with the floating point control unit (30).

Abstract: A process for forming a conductive region without photoresist-related reflective notching damage has a starting step (23) wherein a photoresist layer is formed over a conductive layer (34). The photoresist layer is used to mask the conductive layer. The photoresist layer is lithographically processed and chemically developed to form a masking photoresist region (38) overlying the conductive layer (34). The masking photoresist region has a sidewall and has a reflective notch which results from the lithographic processing. A hardening step, performed in-situ with a plurality of conductive layer etch steps, is used to form an etch-resistant polymer layer (40) on the photoresist sidewalls and on the reflective notch. The conductive layer (34) is etched after the formation of the polymer layer (40) to form a conductive region. The polymer layer (40) reduces an etch rate of the reflective notch and the photoresist sidewall so that the conductive region is formed having no reflective notching etch damage.

Abstract: A ferromagnetic memory circuit (10) and a ferromagnetic memory device (15) which has a substrate (42). Within the substrate (42), a first current electrode (44) and a second current electrode (46) are formed. A control electrode (50) is formed to control current flow between the first and second current electrodes (44 and 46). A ferromagnetic region (68) is used to store a logic value via magnetic flux. Two conductive layers (62 and 70) and a conductive spacer (78) form a sense conductor for device (15). The sense conductor is used to externally provide the logic value stored in the device (15). A conductive layer (82) forms a program/erase line for altering the logic value stored in the device (15). A logic one or a logic zero is stored in ferromagnetic region (68) depending upon a direction and a magnitude of current flow through conductive layer (82).

Abstract: A method for forming an air region or an air bridge overlying a base layer (12). Air regions (20a, 20b, 28a, and 48) are formed overlying the base layer (12) to provide for improved dielectric isolation of adjacent conductive layers, provide air-isolated conductive interconnects, and/or form many other microstructures or microdevices. The air regions (20a, 20b, 28a, and 48) are formed by either selectively removing a sacrificial spacer (16a and 16b) or by selectively removing a sacrificial layer (28, 40). The air regions (20a, 20b, 28a, and 48) are sealed, enclosed, or isolated by either a selective growth process or by a non-conformal deposition technique. The air regions (20a, 20b, 28a, and 48) may be formed under any pressure, gas concentration, or processing condition (i.e. temperature, etc.). The air regions (20a, 20b, 28a, and 48) may be formed at any level within an integrated circuit.

Abstract: A transistor structure (10) has a substrate (12). A first transistor is formed within the substrate (12) having a source region (38), a drain region (30), and a gate electrode formed by a first spacer (26a). A second transistor is formed within the substrate (12) by the source region (38), a drain region (28), and a gate electrode formed by a second spacer (26a). A third transistor is formed overlying the first transistor. The third transistor has a source region (34a), a drain region (34c), a channel region (34b), and a gate electrode formed by the first spacer (26a). A fourth transistor is formed overlying the second transistor. The fourth transistor has a source region (34a), a drain region (34c), a channel region (34b), and a gate electrode formed by the second spacer (26a). The first, second, third, and fourth transistors may be interconnected to form a portion of a compact static random access memory (SRAM) cell.

Abstract: A method for forming a vertical transistor (10) begins by providing a substrate (12). A conductive layer (16) is formed overlying the substrate (12). A first current electrode (26), a second current electrode (30), and a channel region (28) are each formed via one of either selective growth, epitaxial growth, in-situ doping, and/or ion implantation. A gate electrode or control electrode (34) is formed laterally adjacent the channel region (28). A selective/epitaxial growth step is used to connect the conductive layer (16) to the control electrode (34) and forms a control electrode interconnect which is reliable and free from electrical short circuits to the current electrodes (26 and 30). The transistor (10) may be vertically stacked to form compact inverter circuits.

Abstract: A transistor (10 or 11) and method of formation. The transistor (10) has a substrate (12). The substrate (12) has an overlying dielectric layer (14) and an insulated conductive control electrode (16) which overlies the dielectric layer (14). A dielectric region (18) overlies the insulated conductive control electrode (16), and a dielectric region (20) is adjacent to the insulated conductive control electrode (16). A spacer (30) is adjacent to the dielectric region (20). Epitaxial regions (24) are adjacent to the spacer (30) and the spacer (30) is overlying portions of the epitaxial regions (24). A dielectric region (26) overlies the epitaxial regions (24). Highly doped source and drain regions (32) underlie the epitaxial regions (24). LDD regions (28), which are underlying the spacer (30), are adjacent to and electrically connected to the source and drain regions (32).

Abstract: A field effect transistor, FET, (11) having a gate dielectric of varying thickness (14, 24) to improve device performance. The FET (11) is made on a substrate (10) and has a control electrode, or gate (16), and two current electrodes, or source and drain regions (28), which are separated by a channel region. The gate (16) is separated from the channel region by a gate dielectric. The gate dielectric has a centrally located first region that is of a first thickness (14) and a second region which is adjacent a perimeter of the first region that is of a second thickness (24). The second thickness (24) is made greater than the first thickness (14).

Abstract: A capacitor for use in a memory cell (10). A transistor is formed overlying a substrate (10). The transistor has a first current electrode (16) and a second current electrode (18). The current electrodes (16 and 18) are separated by a channel region. A gate electrode (26) is formed overlying the channel region and is physically separated from the channel region by a gate dielectric layer (24). A plug region (32) is formed overlying and electrically connected to the first current electrode (16). An annular high-permittivity dielectric region (33) is formed overlying the transistor and is formed from a high-permittivity dielectric layer (36). A first capacitor electrode is formed via a conductive region (38"), and a second capacitor electrode is formed via a conductive region (38'). The memory cell (10) can be formed as a non-volatile memory cell or a DRAM cell depending upon various properties of the annular high-permittivity dielectric region (33).

Abstract: A method for forming a patterned layer of material begins by providing a substrate (12). A device layer (14) is formed overlying the substrate (12). A layer (16) is formed over the device layer (14). Layer (16) is further characterized as being an inorganic dielectric material, such as a plasma enhanced silicon nitride (PEN) material. A mask (18) is positioned adjacent the layer (16). Ultra-violet (UV) light (20) is selectively exposed to the layer (16) through the mask (18). Exposure from the UV light (20) forms exposed regions (16b) and unexposed regions (16a) of the layer (16). The UV light (20) alters an atomic bonding energy of hydrogen atoms within the exposed regions (16b) while not altering unexposed regions (16a). The layer (16) is exposed to an etchant which etches the exposed regions (16b) and unexposed regions (16a) at different rates. The etching forms a patterned layer from the layer ( 16) which may be used as a masking layer.

Abstract: A transistor (10) has a substrate (12) and a diffusion (14). A gate conductive layer (18) overlies the substrate (12) and has a sidewall formed by an opening that exposes the substrate (12). A sidewall dielectric layer (22) formed laterally adjacent the conductive layer (18) sidewall functions as a gate dielectric for the transistor (10). A conductive region is formed within the opening. The conductive region has a first current electrode region (28) and a second control electrode region (34) and a channel region (30) laterally adjacent the sidewall dielectric layer (22). A plurality of transistors, each in accordance with transistor (10), can be stacked in a vertical manner to form logic gates such as NMOS or PMOS NAND, NOR, and inverter gates, and/or CMOS NAND, NOR, and inverter gates with multiple inputs.

Abstract: A lithographic method using double exposures, physical mask shifting, and light phase shifting is used to form masking features on a substrate masking layer. A first phase shifting mask (11) is placed in a first position adjacent a substrate (10). The substrate (10) is covered by the masking layer. The masking layer is exposed to light, or an equivalent energy source, through the first mask (11) to form a first plurality of unexposed regions of the masking layer. Either a second mask or the first mask (11) is placed adjacent the substrate (10) in a second position which is displaced from the first position in an X direction, a Y direction, and/or a rotational direction. A second exposure is used to form a second plurality of unexposed regions of the masking layer. The first and second pluralities of unexposed regions have common unexposed regions which are used to form the masking features.

Abstract: A semiconductor memory device is formed having a substrate (12). A diffusion (14) is formed within the substrate (12). A first vertical transistor stack (122) is formed. A second vertical transistor stack (124) is formed. The first vertical transistor stack (122) has a transistor (100) underlying a transistor (104). The second vertical transistor stack (124) has a transistor (102) underlying a transistor (106). The transistors (100 and 104) are connected in series, and the transistors (102 and 106) are connected in series. In a preferred form, transistors (100 and 102) are electrically connected as latch transistors for a semiconductor memory device and transistors (106 and 104) are connected as pass transistors. Two vertical stacks (126 and 128) form electrical interconnections (118 and 120) and resistive devices (134 and 138) for the semiconductor memory device.