Abstract: A plurality of integrated circuit devices are bonded to a substrate. Signal traces for corresponding pins of the devices are run to the same location, but are not electrically connected. They are, however, located in close physical proximity at a designated location. At this designated location, a properly shaped and sized contact can be used to contact all of the corresponding traces simultaneously, allowing parallel burn-in of all devices on the substrate to be performed. The devices can still be tested individually after burn-in. Once functionality of the overall subsystem has been confirmed and encapsulation completed, a permanent contact can be made at the designated location to all traces simultaneously so that the devices will be in parallel, and the substrate can be encapsulated to form a completed subsystem.

Abstract: Therefore, according to the present invention, the isolation between adjacent intra-polycrystalline silicon layer components of one or more polycrystalline silicon layers of an integrated circuit device may be enhanced by patterning and then implanting one or more such polycrystalline silicon layers with a high dose of oxygen or nitrogen, in the range of approximately 1.times.10.sup.17 /cm.sup.2 to 1.times.10.sup.19 /cm.sup.2. A post implant anneal is performed in either nitrogen or argon to form a layer of either silicon dioxide or silicon nitride having desirable planar characteristics. The anneal is performed at a temperature range of approximately 1000 to 1400 degrees Celsius.

Abstract: A method and circuit for reading a memory array by utilizing dual dynamic sense amplifiers. A first and a second dynamic sense amplifier are connected to an input line and complementary input line. A latch and a clocking circuit are also connected to the two dynamic sense amplifiers. Initially, an equilibrating signal is input into both sense amplifiers. A first clocking signal and a first isolating signal are then input into the first dynamic sense amplifier. The first clocking signal enables the first sense amplifier to read the data on the input and complementary input lines, while the first isolating signal isolates the first sense amplifier from the input and complementary input lines. An output is then provided to the latch based upon the data read by the first sense amplifier. A second clocking signal and a second isolating signal are then input into the second sense amplifier to enable the second sense amplifier to read the data on the input and complementary input lines.

Abstract: A ring counter includes a plurality of latches forming a shift register. A single bit is sequentially clocked through the shift register, so that only one output is active at any time. A logic circuit is connected to the outputs, and monitors the number of outputs which are active. If more than one output should somehow become active at one time, such as during power up, a reset signal is immediately generated to reset a single bit of the counter active. An external reset signal can also be applied to the logic circuit to force a reset of the counter.

Abstract: A layout and fabrication technique for EPROMs and similar devices includes a preferred technique for partially self-aligning bit line contacts. In addition, a self-aligned, buried Vss line is provided which is in contact with the substrate for its entire length. This provides a highly conductive Vss line, allowing the size of such line to be diminished. The use of a buried Vss contact line and a partially self-aligned bit line contact contributes to a device layout having minimum cell sizes for a given feature size.

Abstract: A tee area is provided from which contestants may hit golf balls toward flag cups located on a plurality of greens. If a contestant hits a golf ball into a flag cup, a ball sensor detects the presence of the golf ball and a remote indicator announces the presence of such a golf ball in the flag cup. Thereafter, an actuator may be utilized to move a door from a closed position to an open position. When such a door is in the open position, the golf ball is permitted to enter a conduit which extends from the flag cup to a remotely located ball receptacle. The actuator then closes the door and a vacuum pump applies a vacuum to the conduit to move the golf ball from the flag cup to the ball receptacle. Air entering the conduit at the flag cup is filtered to prevent debris or other foreign objects from entering the conduit. The ball receptacle may be made from a transparent material so that the golf ball may be identified as belonging to a particular contestant.

Abstract: A method is provided for forming an integrated circuit contact structure. A conductive region is formed on a semiconductor device. Thereafter an insulating layer is formed over the conductive region. An opening is then formed through the insulating region to the conductive region. A thin barrier layer is deposited over the integrated circuit contact structure. A portion of the thin barrier layer is removed by backsputtering the integrated circuit contact structure so that only a thin barrier sidewall remains. Finally, a conductive metal layer is deposited over the integrated circuit contact structure. In one embodiment, the integrated circuit contact structure is baked before the conductive metal layer is deposited.

Abstract: A field oxide structure is formed within a cavity formed in a semiconductor substrate. The cavity has a U-shaped cross section. A layer of thermal oxide covers the walls and bottom of the cavity, and a region of reflowable glass or spin on glass fills the cavity. A layer of undoped oxide, having an upper surface coplanar with the substrate upper surface is formed over the cavity, so that the spin on or reflowable glass is completely surrounded by either thermal oxide or an undoped oxide layer.

Abstract: A method for forming contact vias in a integrated circuit which do not have planarizing material nearby. After a first insulating layer is deposited over the integrated circuit, a planarizing layer is deposited over the first insulating layer. The planarizing layer is etched back and portions of the planarizing layer may remain in the lower topographical regions of the first insulating layer to planarize the surface of the integrated circuit. A first masking layer is then formed over the surface of the integrated circuit. The openings created in the first masking layer have a size which is greater than the size of the contact vias to be formed. The first insulating layer is partially etched into so that portions of the planarizing layer near the locations of the contact vias are removed. The first masking layer is then removed, and a second insulating layer is deposited over the integrated circuit.

Abstract: A programmable semiconductor contact structure and method are provided. A semiconductor substrate has a first patterned conductive layer for forming an interconnect. A first insulating layer overlies the first patterned conductive layer. An opening is formed through the insulating layer to the first patterned conductive layer to form the contact via. A buffer layer overlies portions of the first insulating layer and covers the opening. A second conductive layer overlies the buffer layer. A third conductive layer then overlies the integrated circuit. The buffer layer is a material, such as amorphous silicon, which functions as an anti-fuse and can be programmed by application of a relatively high programming voltage.

Abstract: A memory device provides a control circuit attached to a parity bit position of a memory array. When a selected single bit within an array entry has its value changed without affecting the remaining bits of the entry, the control circuit senses the previous value of the parity bit and internally stores the complement of that value into the parity bit position for that entry. This complementing of the parity bit occurs during the same memory cycle in which the selected bit is changed. Complementing of the parity bit to ensure proper parity function occurs without communication off of the device, and so is completely transparent to the outside world.

Abstract: An SRAM memory cell having first and second transfer gate transistors. The first transfer gate transistor includes a first source/drain connected to a bit line and the second transfer gate transistor has a first source/drain connected to a complement bit line. Each transfer gate transistor has a gate connected to a word line. The SRAM memory cell also includes first and second pull-down transistors configured as a storage latch. The first pull-down transistor has a first source/drain connected to a second source/drain of said first transfer gate transistor; the second pull-down transistor has a first source/drain connected to a second source/drain of said second transfer gate transistor. Both first and second pull-down transistors have a second source/drain connected to a power supply voltage node.

Abstract: Circuits and methods for generating a delay added to a clock signal which clocks an output of a first circuit into an input of a second circuit in a semiconductor device is disclosed. In a first embodiment, a delay circuit is provided for generating an output clock signal for controlling a circuit internal to an integrated circuit, such as a clocked sense amplifier in a memory device, relative to an earlier timing signal, such as a row select signal. The delay circuit is implemented by components having their design parameters, such as transistor dimensions and transistor orientation, corresponding to elements in an active portion of the circuit, such as memory cell transistors.

Abstract: A method for stress testing a memory array in an integrated circuit. Control circuitry selects a plurality of row lines at one time. An overvoltage suitable for stressing the cells of the array is placed on the bit lines. Because a block of cells has been selected, the overvoltage is applied to all cells of the block. The block of cells selected may be either the entire memory array or a portion of the memory array. The selected rows remain selected for the duration of the stress test. Because the overvoltage is applied directly to selected cells, the full overvoltage will be used to stress the transistor gates for the entire test period. In this manner, latent defects within the memory array can be detected.

Abstract: A method for forming field effect devices having lightly doped drain regions requires only a single dope and implant step. After patterning of the polycrystalline silicon gates, sloped sidewall spacers are formed alongside the gates. These spacers have a relatively linear slope from the top corners of the polycrystalline silicon gates to the substrate. A single implant of dopant results in heavily doped regions beyond the sidewall spacers with more lightly, and shallowly, doped regions next to the channel.

Abstract: According to the present invention, a method is provided for forming contact vias in an integrated circuit. Initially, a first protective layer is formed on an insulating layer, and an opening is created through the insulating layer where a contact is to be made. A conductive layer is deposited over the protective layer and partially fills the opening, forming a conductive plug in the opening. A second protective layer is then formed over the conductive plug. Portions of the conductive layer which were formed over the first protective layer are removed. During removal of those portions of the conductive layer, the second protective layer protects the conductive plug from damage. The first and second protective layers are then removed, leaving the conductive plug in the opening in the insulating layer. A conductive contact can now be made by depositing a second conductive layer over the conductive plug.

Abstract: A structure is provided for improving the adhesion between a photoresist layer and a dielectric, and an integrated circuit formed according to the same. A conformal dielectric layer is formed over the integrated circuit. An interlevel dielectric layer is formed over the conformal dielectric layer. The interlevel dielectric layer is doped such that the doping concentration allows the layer to reflow while partially inhibiting the adhesion of the doped layer to photoresist at an upper surface of the doped layer. An undoped dielectric layer is formed over the doped dielectric layer. A photoresist layer is formed and patterned over the undoped dielectric layer which adheres to the undoped dielectric layer. The undoped dielectric, the interlevel dielectric and the conformal dielectric layers are etched to form an opening exposing a portion of an underlying conductive region.

Abstract: A field effect transistor structure includes heavily doped source/drain regions and lightly doped source/drain regions, The lightly doped source/drain regions extend form the source drain regions partway under a sidewall spacer adjacent a gate electrode. Very lightly doped source/drain regions extend the remainder of the way under the sidewall spacers to provide improved transistor characteristics.

Abstract: A push-pull output driver including two transistors in series, one transistor having its body bias controlled by logic circuitry commanded by the driver input. The driver has a pair of transistors in series, the transistor inputs being complementary to create a push-pull amplifier. A switching transistor is controlled by the inverse of the driver input signal and acts as a switch at the pull-up transistor well-tie. When the driver input is high, the switching transistor is off allowing the well-tie to the pull-up transistor to be connected to the driver output. When the input is low, the switching transistor turns on, switching the well-tie of the pull-up transistor to ground. By controlling the body bias of the pull-up transistor in this way, the switching speed of the output driver is significantly increased. When the output driver is in a disabled tri-state mode, the series transistors, and the switching transistor, are turned off.

Abstract: A method is provided for forming isolated regions of oxide of an integrated circuit, and an integrated circuit formed according to the same. A pad oxide layer is formed over a portion of a substrate. A first silicon nitride layer is formed over the pad oxide layer. A polysilicon buffer layer is then formed over the first silicon nitride layer. A second silicon nitride layer is formed over the polysilicon layer. A photoresist layer is formed and patterned over the second silicon nitride layer. An opening is etched through the second silicon nitride layer and the polysilicon buffer layer to expose a portion of the first silicon nitride layer. A third silicon nitride region is then formed on at least the polysilicon buffer layer exposed in the opening. The first silicon nitride layer is etched in the opening. A field oxide region is then formed in the opening.