Abstract: Accelerated failure of processing defects in an integrated circuit memory device is brought about by asserting all wordlines of the memory device to enable all passgates for a plurality of memory cells. Then all bitlines are pulled low to pull low all internal nodes of the plurality memory cells. All active devices in the memory device are turned off or limited to linear region operation. This allows a supervoltage to be applied to the wordlines with internal nodes of the memory cells held low by the bitlines, stressing an oxide barrier between memory cells and wordlines without damaging active devices due to the supervoltage.

Abstract: A method for forming a package for an integrated circuit in which a plurality of conduction paths are formed on a first board and on a second board. Holes are formed in the first board and the second board wherein the holes are adapted for receiving pins. The holes are aligned and the first board is coupled to the second board using an adhesive.

Abstract: A memory cell in which data is written and read from a pass gate. The memory cell has a connection to a first pass gate, connecting the memory cell to a bit line. Additionally, the memory cell has a second pass gate connecting the memory cell to a complementary bit line. The pass gates are controlled by a word line and a complementary word line.

Abstract: The present invention provides an input buffer circuit for reducing false transitions within a circuit. The input buffer circuit includes an input pad for receiving an input voltage, an input buffer having an input and a circuit for modifying a voltage entering the input buffer to track changes in a power supply voltage relative to a voltage at the input pad. The circuit is connected in series between the input pad and the input the input buffer.

Abstract: A method is provided for forming a landing pad of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A plurality of conductive regions are formed over a substrate. A polysilicon landing pad is formed over at least one of the plurality of conductive regions. After the polysilicon is patterned and etched to form the landing pad, tungsten is then selectively deposited over the polysilicon to form a composite polysilicon/tungsten landing pad which is a good etch stop, a good barrier to aluminum/silicon interdiffusion and a good conductor.

Abstract: A resistor structure suitable for use in an SRAM cell is formed from polycrystalline silicon elements. These elements have a cross-section which is less than is normally available for polycrystalline silicon interconnect lines, allowing increased resistance values to be implemented using a lesser amount of surface area. In one embodiment of a resistor, sidewall spacers are formed in a cavity within an insulating layer, and polycrystalline silicon resistive elements are formed in the narrowed region within the cavity. In another embodiment, polycrystalline silicon resistors alongside vertical sidewalls of a cavity are formed using sidewall spacer technology. In either event, the cross-sectional area of the resistors is less than that normally available for a given processing technology, resulting in enhanced resistor values.

Abstract: An SRAM memory cell having first and second transfer gate transistors. The first transfer gate transistor includes a first source/drain connected to a bit line and the second transfer gate transistor has a first source/drain connected to a complement bit line. Each transfer gate transistor has a gate connected to a word line. The SRAM memory cell also includes first and second pull-down transistors configured as a storage latch. The first pull-down transistor has a first source/drain connected to a second source/drain of said first transfer gate transistor; the second pull-down transistor has a first source/drain connected to a second source/drain of said second transfer gate transistor. Both first and second pull-down transistors have a second source/drain connected to a power supply voltage node.

Abstract: A method is provided for forming an improved device dielectric of a semiconductor integrated circuit, and an integrated circuit formed according to the same. For scaling geometries for use in the submicron regime, a composite dielectric layer used as a device dielectric is formed over a plurality of active areas adjacent to a field oxide region. The composite dielectric layer is formed before the field oxide region is formed and comprises a non-porous silicon nitride layer. The non-porous silicon nitride layer preferably comprises a thin deposited silicon nitride layer overlying a thin nitridized region of the substrate. The silicon nitride layer is partially oxidized during the subsequent formation of a field oxide region between the plurality of active areas. An oxide layer may be formed over the silicon nitride layer before the formation of the field oxide region which will then be densified during the field oxide formation.

Abstract: A method for making a thread comprising: feeding at least two drawn, continuous filament starting threads (18, 19), of which at least one is a multi-filament thread, together to an intermingling device (21) to form a single bulked thread of which the filaments of the starting threads are intermingled and looped, and applying a bulk-reducing treatment to the bulked thread characterized in that the bulk-reducing treatment comprises a treatment under tension without the thread being heated.

Abstract: A method of making yarn comprises feeding at least two drawn, continuous filament starting yarns (18, 19), of which at least one is a multifilament yarn, together to an intermingling device (21) to form a single bulked thread of which the filaments of the starting yarns are intermingled and looped, and applying a bulk-reducing treatment to the bulked thread (27), characterized in that the starting yarns are fed to the intermingling device with substantially equal overfeed.

Abstract: A method is provided for forming a planar transistor of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A transistor encapsulated in a dielectric is formed over a substrate. First source and drain regions are formed in the substrate adjacent the transistor. Conductive raised second source and drain regions are formed which overly exposed portions of the first substrate source and drain regions adjacent the transistor. The raised second source and drain regions are formed such that an upper surface of the raised second source and drain regions are substantially planar with an upper surface of the transistor. The dielectric encapsulating the transistor electrically isolates the transistor from the raised second source and drain regions.

Abstract: A method is provided for forming an improved landing pad with barrier of a semiconductor integrated circuit, and an integrated circuit formed according to the same. An opening is formed through a first dielectric layer to expose a portion of a diffused region. A landing pad is formed over the first dielectric layer and in the opening. The landing pad preferably comprises a silicide layer disposed over a barrier layer which is disposed over a polysilicon layer. The landing pad will provide for smaller geometries and meet stringent design rules such as that for contact space to gate. The barrier layer, formed as part of the landing pad, will provide for a uniform and high integrity barrier layer between the diffused region and an overlying aluminum contact to prevent junction spiking. A second dielectric having an opening therethrough is formed over the landing pad. A conductive contact, such as aluminum, is formed in the contact opening.

Abstract: A direct current sum bandgap voltage comparator for detecting voltage changes in a power supply. The direct current sum bandgap voltage comparator includes a summing node, current sources connected to the summing node and the power supply, and an indicator circuit connected to the summing node. Each current source supplies a current to the summing node wherein the summing node voltage level is responsive to the currents supplied. The indicator circuit is responsive to changes in the summing node voltage level and generates at an output a logical signal at one state when the summing node voltage level is greater than a predetermined value and generates the logical signal at the output at another state when the summing node voltage level is less than the predetermined value, the predetermined value corresponding to a preselected power supply voltage.

Abstract: A method for forming sloped contact corners of an integrated circuit, and an integrated circuit formed according to the same, is disclosed. A first oxide layer is formed over the integrated circuit. An insulating layer is formed over the oxide layer. The oxide and insulating layers are then patterned and etched to form a contact opening to expose a conductive region underlying a portion of the oxide layer. A second oxide layer is formed in the bottom of the contact opening. The insulating layer is then reflowed to form rounded contact corners after which the second oxide layer is removed.

Abstract: A structure useful during the fabrication of semiconductor integrated circuits. At least one layer is formed over an insulating layer, and an opening formed to an underlying substrate. A conductive layer is formed over the at least one layer, which simultaneously forms a conductive plug in the bottom of the opening. An insulating layer plug is formed over the conductive plug to provide protection while the conductive layer on the at least one layer is removed.

Abstract: An apparatus and method for switching between two power supplies, a primary power supply and a secondary power supply. The present invention generates a first reference voltage using the voltage of the primary power supply and the secondary power supply, wherein the primary power supply voltage is variable. The present invention also generates a second reference voltage based on the voltage of the primary power supply. The first and second reference voltages each have a different slope and the crossing point between these two reference voltages indicate that a switch between the primary power supply and the secondary power supply should occur.

Abstract: A method is provided for forming a planar surface of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A gate oxide layer is formed over a silicon substrate. A first polysilicon layer is formed over the gate oxide layer and a nitride layer is formed over the first polysilicon layer. The first polysilicon and nitride layers are then patterned and etched to form an opening which exposes a portion of the gate oxide layer. An oxidation step is then performed to form a field oxide region in the opening. The field oxide region is formed to a thickness having an upper surface substantially planar with an upper surface of the first polysilicon layer. The nitride layer is then removed and the gate oxide and first polysilicon layers are patterned and etched to form a gate electrode and an interconnect.

Abstract: A semiconductor read only memory device includes memory cells arranged in a matrix of rows and columns; word lines crossing the matrix, wherein one word line is connected to each row of memory cells; and bit lines interdigitated with column lines and positioned such that each column of memory cells is between a bit line and a column line. The matrix is subdivided into cells, where each cell has four memory cells arranged symmetrically about a bit line in two rows and two columns. All four of the cells are connected to the bit line at a common electrical node, wherein selected cells are connected to a column line. The memory device also includes a row select driver for selecting memory cells in a single row; a column select driver for selecting a single column line; and circuitry for selecting one of the bit lines adjacent to a column line.

Abstract: A method for fabricating an integrated circuit transistor begins with forming a gate electrode over an insulating layer grown on a conductive layer. Sidewall spacers are formed alongside vertical edges of the gate electrode and a mask is applied to a drain region. A relatively fast-diffusing dopant is then implanted into a source region in the conductive layer. Thereafter, the mask is removed and the drain region is implanted with a relatively slow-diffusing dopant. Finally, the conductive layer is annealed, causing the relatively fast-diffusing dopant to diffuse beneath the source sidewall spacer to a location approximately beneath the vertical edge of the source side of the gate electrode, and causing the relatively slow-diffusing dopant to extend beneath the drain sidewall spacer a lesser distance, so that the drain junction is laterally spaced from underneath the gate electrode.