Abstract: A method is provided for forming a landing pad of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A plurality of conductive regions are formed over a substrate. A polysilicon landing pad is formed over at least one of the plurality of conductive regions. After the polysilicon is patterned and etched to form the landing pad, tungsten is then selectively deposited over the polysilicon to form a composite polysilicon/tungsten landing pad which is a good etch stop, a good barrier to aluminum/silicon interdiffusion and a good conductor.

Abstract: A gate structure in a transistor and method for fabricating the structure. A gate structure is formed on a substrate. The gate structure includes three layers: an oxide layer, a nitride layer and a polysilicon layer. The oxide layer is located on the substrate, the nitride layer is located on the oxide layer, and the polysilicon layer is located on the nitride layer. The gate structure is reoxidized to form a layer of oxide over the gate structure.

Abstract: A method for creating isolation structures in a substrate without having to increase the field implant doses to prevent punch through. This particular advantage is achieved by first growing a pad oxide on the substrate. Polysilicon is deposited on top of the pad oxide layer. Next, silicon nitride, used for masking, is deposited on the polysilicon layer. An opening, also called an isolation space, is etched into the three layers, exposing part of the substrate. A first field oxide is grown in the opening. This first field oxide layer is etched to expose a portions of the substrate along the edge of the field oxide region. Then, trenches are etched into the exposed portions of the substrate, and field implantation of dopants is performed. After implantation, a second field oxide layer is grown. The silicon nitride, polysilicon, and pad oxide are then removed, resulting in the isolation structure of the present invention.

Abstract: A pulse generator for use in generating pulses at different locations within a circuit has a first circuit 501 for a time dependent operation after receipt of a first input pulse and a second circuit 502 for carrying out a time dependent operation after receipt of a second input pulse after the first input pulse. A third circuit 503 is responsive to each of the first and second circuits 501,502 reaching respective predetermined conditions so that an output pulse is produced by the third circuit 503 at a time dependent on the average durations of operation of the first and second circuits 501 and 502.

Abstract: A method is provided for forming an improved planar structure of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A field oxide is grown across the integrated circuit patterned and etched to form an opening with substantially vertical sidewalls exposing a portion of an upper surface of a substrate underlying the field oxide where an active area will be formed. A gate electrode comprising a polysilicon gate electrode and a gate oxide are formed over the exposed portion of the substrate. The polysilicon gate has a height at its upper surface above the substrate at or above the height of the upper surface of the field oxide. The gate electrode preferably also comprises a silicide above the polysilicon and an oxide capping layer above the silicide. LDD regions are formed in the substrate adjacent the gate electrode and sidewall spacers are formed along the sides of the gate electrode including the silicide and the capping layer.

Abstract: Therefore, according to the present invention, the isolation between adjacent intra-polycrystalline silicon layer components of one or more polycrystalline silicon layers of an integrated circuit device may be enhanced by patterning and then implanting one or more such polycrystalline silicon layers with a high dose of oxygen or nitrogen, in the range of approximately 1.times.10.sup.19 /cm.sup.2 to 1.times.10.sup.17 /cm.sup.2. A post implant anneal is performed in either nitrogen or argon to form a layer of either silicon dioxide or silicon nitride having desirable planar characteristics. The anneal is performed at a temperature range of approximately 1000 to 1400 degrees Celsius.

Abstract: An interconnect structure, and method for forming same, is suitable for use in integrated circuits such as SRAM devices. The structure uses masking of a polycrystalline silicon interconnect level to move a P-N junction to a region within a polycrystalline silicon interconnect line, rather than at the substrate. This P-N junction can then be shorted out using a refractory metal silicide formed on the polycrystalline silicon interconnect structure.

Abstract: A gate structure in a transistor and method for fabricating the structure. A gate structure is formed on a substrate. The gate structure includes three layers: an oxide layer, a nitride layer and a polysilicon layer. The oxide layer is located on the substrate, the nitride layer is located on the oxide layer, and the polysilicon layer is located on the nitride layer. The gate structure is reoxidized to form a layer of oxide over the gate structure.

Abstract: A method for forming an aluminum contact through an insulating layer includes the formation of an opening. A barrier layer is formed, if necessary, over the insulating layer and in the opening. A thin refractory metal layer is then formed over the barrier layer, and aluminum deposited over the refractory metal layer. Proper selection of the refractory metal layer and aluminum deposition conditions allows the aluminum to flow into the contact and completely fill it. Preferably, the aluminum is deposited over the refractory metal layer without breaking vacuum.

Abstract: A method for fabricating conductive structures in integrated circuits. A conductive layer is formed over an underlying region in an integrated circuit. The conductive layer is then doped with impurities, and a thin amorphous silicon layer is formed over the conductive layer. A photoresist layer is then deposited and exposed to define a masking pattern. During exposure of the photoresist layer, the amorphous silicon layer acts as an anti-reflective layer. Portions of the photoresist layer are then removed to form a masking layer, and the insulating layer and amorphous silicon layer are then etched utilizing the masking layer to form conductive structures. During subsequent thermal processing, impurities from the conductive layer diffuse into the amorphous silicon layer causing the amorphous silicon layer to become conductive.

Abstract: A zero power circuit includes an upper power supply voltage pad, battery pad, a power control circuit, and a suppression circuit. The power control circuit provides power to the zero power circuit by switching between the battery pad and the upper power supply voltage pad. The suppression circuit is connected in series between the power control circuit and the battery pad. The suppression circuit includes a resistor connected in series between the battery pad and the power control circuit, wherein current flowing through the transistor during a latch condition causes the voltage to drop across the resistor, suppressing the latchup condition to the battery pad. The suppression circuit also includes a transistor connected in parallel with the resistor, the transistor having a gate, wherein a first signal applied to the gate turns off the transistor and a second signal applied to the gate turns on the transistor, wherein the resistor is shorted when the transistor is turned on.

Abstract: The die has first and second die halves, each die half having a plurality of cavities that, when the die halves are in a closed position, align with the cavities in the other die half, thus defining a plurality of voids that define the objects to be formed. Each cavity is aspherical in that the slope of the cavity is never perpendicular to the front surface of the die half, thus facilitating the removal of the objects from the die. A spacing between the front surfaces of the die halves during the injection step of the cycle helps to increase the number of parts that properly release from the die.

Abstract: A method is provided for forming a substantially planarized surface of an integrated circuit, and an integrated circuit formed according to the same. A conductive area is formed over a portion of a dielectric region. A first spin-on-glass layer is formed over the conductive area and exposed dielectric region. A second spin-on-glass layer is formed over the first spin-on-glass layer; wherein the second spin-on-glass layer has a slower etch rate than the first spin-on-glass layer. A partial etchback of the first and second spin-on-glass layers is performed forming a substantially planar surface.

Abstract: A method and circuit for significantly reducing a delay added to a clock signal which clocks an output of a first circuit into an input of a second circuit in a semiconductor device. An output of a first circuit is connected to a data line. The first circuit is designed with elements having a selected set of design parameters, such as transistor dimensions and transistor orientation. A second circuit is connected to the data line and also receives a clock signal generated by a signal delay circuit. The signal delay circuit receives an output enable signal, and after a delay period, produces the clock signal in response to the output enable signal. At least a portion of the signal delay circuit utilizes elements having the selected set of design parameters utilized in the first circuit.

Abstract: A semiconductor read only memory device includes memory cells arranged in a matrix of rows and columns; word lines crossing the matrix, wherein one word line is connected to each row of memory cells; and bit lines interdigitated with column lines and positioned such that each column of memory cells is between a bit line and a column line. The matrix is subdivided into cells, where each cell has four memory cells arranged symmetrically about a bit line in two rows and two columns. All four of the cells are connected to the bit line at a common electrical node, wherein selected cells are connected to a column line. The memory device also includes a row select driver for selecting memory cells in a single row; a column select driver for selecting a single column line; and circuitry for selecting one of the bit lines adjacent to a column line.

Abstract: A method for forming a contact via in an integrated circuit includes the formation of an aluminum conductive element on an integrated circuit device. A conformal insulating layer is then deposited over the device. Using a masking layer, an anisotropic etch is performed to open a via through the conformal insulating layer. During the anisotropic etch, polymers are created from the resist and etch chemistry and adhere to the sidewalls of the via. A resist developer containing Tetra Methyl Amonium Hydroxide is used to remove the polymers from the via. A contact may now be formed by depositing conductive material into the via.

Abstract: A structure and method for fabricating intergrated circuit which provides for the detection of residual conductive material. A first conductive layer is deposited over the intergrated circuit and patterned to define a first interconnect layer. An insulating layer in then formed over the integrated circuit. A second conductive layer is then deposited and patterned to define a second interconnect layer. Residual conductive material can be formed during pattering of the second interconnect layer when portions of the second conductive layer remain adjacent to the vertical sidewalls of the first interconnect layer. To make the residual conductive material easier to detect, the conductivity of the residual conductive material is increased by either implanting impurities into the integrated circuit or siliciding the residual conductive material with a refractory metal.

Abstract: An integrated circuit structure contains both highly resistive regions and highly conductive interconnect regions in a single layer of polycrystalline silicon. The resistive regions have a smaller cross section than the interconnect regions as a result of partial oxidation. Their thickness and width are reduced from that of the interconnect regions. The partial oxidation leaves an oxide region, derived from polycrystalline silicon, on both the top and sides of the resistive regions.

Abstract: A structure and method for forming contact structures in integrated circuits. A buffer layer is formed over an underlying conductive element. A first conductive layer is then deposited over the buffer layer and patterned to define a first interconnect layer. While the first interconnect layer is patterned, the buffer layer protects the underlying conductive element from damage. Portions of the buffer layer which are not covered by the first interconnect layer are then removed, and a second conductive layer is deposited over the integrated circuit. The second conductive layer is then anisotropically etched to form conductive sidewall spacers alongside the vertical sidewalls of the first interconnect layer, where at least one of the conductive sidewall spacers makes electrical contact with the underlying conductive element. Therefore, a conductive contact is made between the underlying conductive element and the first interconnect layer through at least one of the conductive sidewall spacers.

Abstract: A method is provided for forming a contact opening or via of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A first metal region is formed over an underlying region. A first insulating layer is formed over the integrated circuit. A second insulating layer is then formed over the first insulating layer. A portion of the second insulating layer is etched to expose a portion of the first insulating layer wherein the exposed first insulating layer and the remaining second insulating layer form a substantially planar surface. A metal oxide layer is formed over the exposed first insulating layer and the remaining second insulating layer. A photoresist layer is formed and patterned over the metal oxide layer. The metal oxide layer is then selectively etched to form a via exposing a portion of the first insulating layer. The first insulating layer in the via is then selectively etched to expose a portion of the first metal region.