Abstract: A method is provided for forming a radiation hard dielectric region of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A field oxide region, a gate oxide layer and an interlevel dielectric layer are formed over the integrated circuit. Silicon ions are implanted separately into the field oxide region, gate oxide layer and interlevel dielectric layer to a sufficient dosage of less than or equal to approximately 1.times.10.sup.14 /cm.sup.2 to form electron traps to capture radiation induced electrons. This method allows for selective enhancement of radiation hardness of a portion of a circuit, thus providing an on-chip "dosimeter" which can be used to compensate the circuit for the loss of performance due to ionizing radiation.

Abstract: A regulated power supply provides a regulated supply voltage at a preselected level under normal operating conditions. When power demands of the circuitry driven by the supply requires a higher voltage, the supply adapts to supply such a higher voltage. Such a supply can be used with automotive electronic circuitry, and can supply voltages up to approximately the voltage available on an automobile battery when such higher power demands occur. The higher supply voltages remain regulated, and return to normal levels when the extra power requirement is removed.

Abstract: A dual-port data cache is provided having one port dedicated to servicing a local processor and a second port dedicated to servicing a system. The dual-port data cache is also capable of a high speed transfer of a line or lines of entries by placing the dual-port data cache in "burst mode." Burst mode may be utilized with either a read or a write operation. An initial address is latched internally, and a word line in the memory array is activated during the entire data transfer. A control circuit is utilized to cycle through and access a number of column addresses without having to provide a separate address for each operation.

Abstract: A method is provided for forming a polysilicon buried contact of an integrated circuit, and an integrated circuit formed according to the same. A field oxide region is formed over a portion of a substrate leaving an exposed active region. An oxide layer is formed over the active region. A first photoresist layer is formed and patterned over the first silicon layer. The first silicon layer is then etched to form an opening therethrough to expose a portion of the oxide layer. The oxide layer is etched through the opening to expose a portion of the substrate. A conductive etch stop layer is formed over the exposed portion of the substrate and the first photoresist layer. The first photoresist layer and the etch stop layer overlying the first photoresist layer are then removed. A second silicon layer is formed over the first silicon layer and the remaining etch stop layer. A second photoresist layer is formed and patterned over the second silicon layer.

Abstract: A method is provided for patterning a submicron semiconductor layer of an integrated circuit, and an integrated circuit formed according to the same. A first conductive structure is formed over the integrated circuit. A dielectric is formed over the first conductive structure having a contact opening exposing a portion of the underlying first conductive layer. A barrier layer is formed in the bottom of the contact opening. A second, substantially conformal conductive layer is formed by chemical vapor deposition over the dielectric layer; along the sidewalls and in the bottom of the contact opening. A third conductive layer is then formed over the second conductive layer wherein the third conductive layer does not fill the contact opening. The second and third conductive layers are etched to form an interconnect substantially over the contact opening.

Abstract: A method and apparatus for testing and programming signal timing are disclosed which can be incorporated into an integrated circuit device utilizing on-chip timed command signals and pulses. The method of the invention enables nonpermanent testing and retesting of a device at various operational speeds during production testing. During retesting, temporary signal delays are selectively introduced into the circuit of a device which failed a previous test due to non-repairable errors. Once a device passes the production test error-free or with repairable errors, the temporary signal delays are permanently programmed into the device. Specifically, the method utilizes one or a plurality of mode control circuits and test voltage input terminals to nonpermanently select signal delays which may be identified and permanently enabled at a later time.

Abstract: A method is provided for patterning a submicron semiconductor layer of an integrated circuit, and an integrated circuit formed according to the same. A first conductive structure is formed over the integrated circuit. A dielectric is formed over the first conductive structure having a contact opening exposing a portion of the underlying first conductive layer. A barrier layer is formed in the bottom of the contact opening. A second, substantially conformal conductive layer is formed by chemical vapor deposition over the dielectric layer; along the sidewalls and in the bottom of the contact opening. A third conductive layer is then formed over the second conductive layer wherein the third conductive layer does not fill the contact opening. The second and third conductive layers are etched to form an interconnect substantially over the contact opening.

Abstract: A system for providing a CMOS NOR function that is distributed across a number of devices located on different chips. Specifically the present invention may be implemented in tag RAMs to provide expanded addressing. In other words, larger addresses may be processed using the present invention. This function is provided by using some transistors on each chip as part of the CMOS NOR gate.

Abstract: A master enable circuit is provided which receives multiple enable signal inputs while matching the redundant decoder enable delay with decoder enable delay. A master enable circuit contains a hard coded master fuse, driver transistor, and a multiple input logic gate. A blown master fuse forces the driver output to an enable state. When the proper select signals are then received by the logic gate, the decoder is enabled to allow selection of the redundant row without introducing a mismatch of redundant and normal line select times.

Abstract: A method is provided for forming isoplanar isolated regions in an integrated circuit, and an integrated circuit formed according to the same. According to a first disclosed embodiment, a first epitaxial layer is formed over a substrate, the substrate having a (100) crystal orientation. A first masking layer is formed over the first epitaxial layer. The first masking layer is patterned and the first epitaxial layer is etched to form openings. The sidewalls of these openings have a (111) crystal orientation. The first masking layer is then removed and a second masking layer is formed in the openings. The first epitaxial layer is anodized and oxidized. The second masking layer is removed and a second epitaxial layer is formed in the openings. According to an alternate embodiment, after the first epitaxial layer is anodized, the second epitaxial layer is formed in the openings and the first epitaxial layer is then oxidized.

Abstract: A memory includes a number of memory groups. Each memory group includes a set of memory subgroups and a number of data bus drivers, wherein each data bus driver has a true input and a complement input and a true output and a complement output. The true and complement inputs are connected to a memory subgroup by at least one sense amplifier. A true connection point also is included in the memory, and the true output of one of the data bus drivers from each of the memory groups are connected together at the connection point, and a "wired" configuration is created. In addition, the memory includes a complement connection point, wherein the complement output of one of the data bus drivers from each of the memory groups are connected together at the connection point, creating a "wired" configuration. The memory also has a data bus circuit with a true input connected to the true connection point and a complement input connected to the complement connection point and a first circuit.

Abstract: A method for forming field oxide regions on an integrated circuit device includes the steps of providing doped regions for formation of active devices. After the doped regions have been formed, a thick field oxide layer is grown over the entire surface of the device. Field oxide regions are then defined using masking and anisotropic etching steps which provide approximately vertical sidewalls for the field oxide regions, and which do not result in the formation of bird's beaks. Since the active regions are defined prior to formation of the field oxide regions, the active regions extend under the field oxide regions and do not give rise to edge effects.

Abstract: A method is provided for patterning a submicron semiconductor layer of an integrated circuit, and an integrated circuit formed according to the same. A conductive structure is formed on the integrated circuit. A dielectric layer is formed over the integrated circuit. A contact opening is formed in the dielectric layer exposing a portion of the underlying first conductive structure. A barrier layer is formed on the dielectric layer and in the contact opening. A substantially conformal layer is formed over the barrier layer and in the contact opening. The conformal layer is partially etched away wherein the conformal layer remains only in a bottom portion of the contact opening. A second conductive layer is formed over the barrier layer and the remaining conformal layer.

Abstract: A method is provided for forming a transistor spacer etch endpoint structure of an integrated circuit, and an integrated circuit formed according to the same. A gate is formed over a portion of a substrate. A dielectric layer is formed over the integrated circuit and an oxide layer is formed over the dielectric layer. the oxide layer is patterned and etched to form sidewall oxide spacers on each side of the gate and over a portion of the dielectric layer. The dielectric layer not covered by the sidewall oxide spacers is then removed.

Abstract: The invention may be incorporated into a method for forming a vertically oriented semiconductor device structure, and the semiconductor structure formed thereby, by forming a first transistor over a portion of a substrate wherein the first transistor has a gate electrode and a source and drain regions. First and second interconnect regions are formed over a portion of the gate electrode and a portion of the source and drain regions of the first transistor, respectively. A source and drain region of a second transistor is formed over the second interconnect. A Vcc conductive layer is formed over a portion of the source and drain region of the second transistor which is formed over the second interconnect.

Abstract: A method and apparatus are provided for operating a small diameter thermal spray gun to thermal spray a coating onto a substrate. A liquid fuel and regeneratively heated air are swirled together within a mixing chamber, passed through a restricter plate orifice, and then passed into the combustion chamber to atomize the liquid fuel and mix the liquid fuel with the regeneratively heated air. The liquid fuel is then burned within a combustion chamber of a small diameter thermal spray gun to generate a high energy flow stream, into which a coating material is injected. The combustion chamber includes an inner sleeve with cooling ports which pass cooling air laterally therethrough. A flow nozzle directs the high energy flow stream towards the substrate. The flow nozzle transfers a heat flow from a first portion of the high energy flow stream to a second portion of the high energy flow stream, and provides a thermal barrier to retain heat within the high energy flow stream.

Abstract: A cache tag memory device having a memory array comprising a first single-port memory array, a second single-port memory array, and a dual-port memory array. A first port, accessed by a local processor, may read from and write to its corresponding single-port memory array and the dual-port memory array. A second port, accessed through a global system bus, may also read from and write to its corresponding second single-port memory array and the dual-port memory array. Both ports operate asynchronously relative to each other. Status bits indicating the status of the entries in the first and second single-port memory arrays are stored in the dual-port memory array and may be altered by the global system while the local processor is performing its operations.

Abstract: A method is provided for forming a via for multilevel metallization of an integrated circuit, and an integrated circuit formed according to the same. A first conductive layer is formed over the integrated circuit. A first dielectric layer is then, formed over the first conductive layer. A second dielectric layer over the first dielectric layer and a second conductive layer is formed over the second dielectric layer. A photoresist layer is formed and patterned over the second conductive layer to expose a portion of the second conductive layer. The second conductive layer is etched to form an opening exposing a portion of the second dielectric layer. The second dielectric layer is then etched in the opening to form partially sloped sidewalls sloping outward at an upper surface of the dielectric layer. The photoresist layer is removed. The remaining second dielectric layer and the first electric layer is then anisotropically etched in the opening exposing the portion of the first conductive layer in the opening.

Abstract: A method is provided for forming an improved poly-buffered LOCOS process by forming a pad oxide layer over a substrate. A first nitride layer is formed over the pad oxide layer and a polysilicon layer is formed over the first nitride layer. A second nitride layer is formed over the polysilicon layer. An opening is etched through the second nitride layer, the polysilicon layer, the first nitride layer and the pad oxide layer to expose a portion of the underlying substrate. A field oxide region is then formed in the opening.

Abstract: A first-in first-out (FIFO) memory includes flag generation circuitry indicating the relative fullness of the memory. A write and a read counter count the number of read and write clock signals used to read to and write from the memory. A subtractor circuit receives the values in the counters as inputs, and generates a difference signal as an output. This difference signal is then compared to a program value, and a flag generated indicating the relative magnitudes of the difference value and the program value. Several different program values can be utilized to generate several different flags for the memory.