Abstract: A polysilicon thin film transistor (TFT) may include a substrate, at least one insulating layer, a semiconductor layer, a gate electrode, a source electrode, a drain electrode, and a heat retaining layer formed to contact the semiconductor layer. The heat retaining layer may reduce and/or prevent a reduction in a melt duration time of amorphous silicon during a crystallization process for forming a polysilicon layer of the TFT.
Type:
Grant
Filed:
August 22, 2006
Date of Patent:
September 28, 2010
Assignee:
Samsung Mobile Display Co., Ltd.
Inventors:
Jae Kyeong Jeong, Hyun Soo Shin, Yeon Gon Mo
Abstract: A method of programming a flash memory includes programming memory cells connected to a selected word line by applying a first voltage to the selected word line and a second voltage to non-selected word lines, the second voltage being lower than the first voltage, lowering the first voltage of the selected word line to a third voltage after programming the memory cells connected to the selected word line, the third voltage being lower than the first voltage, and recovering a fourth voltage of the selected word line and the non-selected word lines, the fourth voltage being lower than the second and third voltages.
Abstract: In a semiconductor device, and a method of fabricating the same, the semiconductor device includes a protrusion extending from a substrate and a selective epitaxial growth (SEG) layer surrounding an upper portion of the protrusion, the SEG layer exposing sidewalls of a channel region of the protrusion.
Abstract: A method of fabricating a semiconductor device includes sequentially forming a first pattern and a second pattern on a substrate, the second pattern being a non-single-crystalline semiconductor stacked on the first pattern, wherein a portion of the substrate is exposed adjacent to the first and second patterns, forming a non-single-crystalline semiconductor layer on the substrate, the semiconductor layer contacting the second pattern and the exposed portion of the substrate, and, using the substrate as a seed layer, changing the crystalline state of the semiconductor layer to be single-crystalline and changing the crystalline state of the second pattern to be single-crystalline.
Abstract: A thin film transistor (TFT), including a substrate, an active layer and a gate electrode on the substrate, and a first gate insulating layer and a second gate insulating layer between the active layer and the gate electrode. Each of the first gate insulating layer and the second gate insulating layer may have a thickness between approximately 200 ? and approximately 400 ?, inclusive.
Type:
Grant
Filed:
July 28, 2008
Date of Patent:
September 21, 2010
Assignee:
Samsung Mobile Display Co., Ltd.
Inventors:
Moo-Jin Kim, Cheol-Su Kim, Ki-Yong Lee, Kyoung-Bo Kim
Abstract: A method for manufacturing an indium tin oxide (ITO) target and methods for preparing indium oxide powder (In2O3) and tin oxide powder (SnO2). The method for manufacturing an ITO (indium tin oxide) target includes preparing an In2O3 powder having a surface area of about 10-18 m2/g and an average particle diameter of between about 40 to 80 nm; preparing a SnO2 powder having a surface area of about 8-15 m2/g and an average particle diameter of about 60-100 nm; molding a mixture of the In2O3 powder and the SnO2 powder; and sintering the mixture at atmospheric pressure under oxidation atmosphere. The ITO target is applicable for a high-quality, transparent electrode for a display, such as a liquid crystal display, electroluminescent display, or field emission display.
Abstract: A method for manufacturing an array plate for biomolecules includes coating a surface of a substrate with a hydrophobic material to form a hydrophobic layer having initial hydrophobic properties, etching the hydrophobic layer through an etch mask placed thereon to form a hydrophilic binding site, removing the etch mask, and processing the remaining region of the hydrophobic layer to recover the initial hydrophobic properties. A method for manufacturing a biochip using this array plate, includes processing the surface of the hydrophilic binding site of the array plate to increase an affinity of biomolecules to the hydrophilic binding site, and applying a solution containing biomolecules to the surface of the hydrophilic binding site.
Type:
Grant
Filed:
May 15, 2003
Date of Patent:
September 14, 2010
Assignee:
Samsung Electronics Co., Ltd.
Inventors:
Woon-bae Kim, Chang-ho Cho, Kae-dong Back, Hwan-young Choi
Abstract: An electron emission device includes a first plate and a second plate spaced apart and facing each other, a first electrode having an electron emission source electrically coupled thereto, the electron emission source including a carbon-based material and a ferroelectric material, a second electrode disposed adjacent to the first electrode, and a phosphor layer disposed so as to receive electrons emitted by the electron emission source.
Type:
Grant
Filed:
October 31, 2006
Date of Patent:
September 14, 2010
Assignee:
Samsung SDI Co., Ltd.
Inventors:
Hee-Sung Moon, Jae-Myung Kim, So-Ra Lee
Abstract: A paste composition for an electrode includes a conductive material, a colored glass frit, the glass frit exhibiting a blackness (L*) value of about 85 or less, a binder, and a solvent.
Type:
Grant
Filed:
April 17, 2008
Date of Patent:
September 14, 2010
Assignee:
Cheil Industries, Inc.
Inventors:
Sang Hee Park, Deok Young Choi, Byung Cheol Lee, Hee In Nam, Hyun Don Kim
Abstract: A magnetoresistive random access memory (RAM) may include a plurality of variable resistance devices, a plurality of read bitlines electrically connected to respective variable resistance devices, and a plurality of write bitlines alternating with the read bitlines. The magnetoresistive RAM may be configured to apply a first write current through a first write bitline adjacent to a first variable resistance device when writing a first data to the first variable resistance device, and apply a first inhibition current through a second write bitline adjacent to a second variable resistance device, the second variable resistance device being adjacent to the first write bitline, and between the first write bitline and the second write bitline, and the first write current and the first inhibition current flowing in a same direction.
Abstract: A display device which may include a bottom chassis receiving a display panel, at least one printed circuit board mounting parts for controlling the display panel, and a reinforcing chassis attached to the printed circuit board.
Type:
Grant
Filed:
November 22, 2006
Date of Patent:
September 7, 2010
Assignee:
Samsung Mobile Display Co., Ltd.
Inventors:
Jin Seok Jang, Jae Ho Jung, Yong Seok Kim, Hyo Shin Song, Hwan Soo Lim
Abstract: A piezoelectric ink-jet printhead and a method for manufacturing the same, wherein the piezoelectric ink-jet printhead is formed by stacking three monocrystalline silicon substrates on one another and adhering them to one another. The three substrates include an upper substrate, through which an ink supply hole is formed and a pressure chamber is formed on a bottom surface thereof; an intermediate substrate, in which an ink reservoir and a damper are formed; and a lower substrate, in which a nozzle is formed. A piezoelectric actuator is monolithically formed on the upper substrate. A restrictor, which connects the ink reservoir to the pressure chamber in flow communication, may be formed on the upper substrate or intermediate substrate.
Abstract: A liquid crystal display device includes a black matrix between first and second substrates, the black matrix having openings defined therein, color filters between the first and second substrates and aligned with the openings defined in the black matrix, the color filters including first filters having a first color, second filters having a second color, and third filters having a third color; and spacers configured to maintain a predetermined cell gap. The second filters have a recess, such that the second filters have an area that is less than an area of the first filters, the spacers are aligned with regions of the black matrix adjacent to the recesses in the second filters, and alignment layers are on the first and second substrates.
Abstract: A signal processing apparatus of an optical disk recording/reproducing apparatus and a signal processing method performed thereby are provided. The signal processing apparatus may include an operational data generation unit for receiving digital signals, filtering received digital signals and outputting filtered signals as operational data and a data arithmetic-operation unit for performing an arithmetic operation on the operational data output by the operational data generation unit in response to a command.
Abstract: A sub-wavelength anti-reflective diffractive structure is incorporated with a base diffractive structure having a small period to form a high efficiency diffractive structure. In the high efficiency diffractive structure, the anti-reflective structure and/or the base diffractive structure are altered from their ideal solo structure to provide both the desired performance and minimize reflections.
Abstract: A shift register, including first through third output nodes and first through third input lines for first through third clock signals, a fourth input line adapted to supply a start pulse or an output signal, a voltage level controller coupled between the second and fourth input lines, the voltage level controller being adapted to control voltage levels of the first and second output nodes, a first transistor coupled between a first power supply and the third output node, the third output node being an output node of the stage, a second transistor coupled between the third output node and the third input line, and a third transistor coupled between the first output node and a second power supply.
Abstract: A method of manufacturing a semiconductor device includes forming a diffusion barrier layer on a substrate, and forming at least two features on the substrate such that the diffusion barrier layer is respectively disposed between each feature and the substrate and contacts the at least two features. A first impurity region of the substrate contains impurities of a first type, a second impurity region of the substrate contains impurities of a second type, different from the first type, a first feature of the at least two features is in the first impurity region, and a second feature of the at least two features is in the second impurity region, such that the second feature is electrically isolated from first feature by the different impurity regions.
Type:
Grant
Filed:
March 4, 2008
Date of Patent:
August 31, 2010
Assignee:
Samsung Electronics Co., Ltd.
Inventors:
Un Byoung Kang, Yong Hwan Kwon, Chung Sun Lee, Woon Seong Kwon, Hyung Sun Jang
Abstract: An EL display, including a substrate having a pixel region and a non-pixel region, at least one light emitting diode disposed on the pixel region of the substrate, a sealant disposed on the non-pixel region of the substrate, an oxygen generating layer, an absorbent layer laminated onto the oxygen generating layer, and a cap adhered to the sealant, such that the at least one light emitting diode, the oxygen generating layer, and the absorbent layer are enclosed between the cap and the substrate.
Abstract: A flash memory device includes a program data buffer configured to buffer program data to be programmed in a memory cell array, and a verify data buffer configured to compare verify data to confirm whether the program data is accurately programmed in the memory cell array, wherein at least a portion of the verify data buffer is selectively enabled as a verify data buffer or a program data buffer responsive to a buffer control signal.
Abstract: A method of depositing a thin film may include providing a wafer into a thin film apparatus, rotating the wafer, flowing a plasma across the wafer from edge to edge, depositing a first thin film on the wafer, creating a temperature gradient within the thin apparatus, and depositing a second thin film on the wafer. The temperature gradient may include having the temperature at the center of the wafer being higher than the temperature at the edges of the wafer.