Abstract: An emitter for an electron-beam projection lithography system includes a photoconductor substrate, an insulating layer formed on a front surface of the photoconductor substrate, a gate electrode layer formed on the insulating layer, and a base electrode layer formed on a rear surface of the photoconductor substrate and formed of a transparent conductive material. In operation of the emitter, a voltage is applied between the base electrode and the gate electrode layer, light is projected onto a portion of the photoconductor substrate to convert the portion of the photoconductor substrate into a conductor such that electrons are emitted only from the partial portion where the light is projected. Since the emitter can partially emit electrons, partial correcting, patterning or repairing of a subject electron-resist can be realized.

Abstract: A gas injection apparatus for injecting a reactive gas into a reaction chamber of a semiconductor processing system includes an injector in contact with an inner surface of a wall of the reaction chamber. The injector has a plurality of nozzles through which the reactive gas is injected into the reaction chamber. A gas inlet penetrates the wall of the reaction chamber. A manifold is disposed between the wall of the reaction chamber and the injector, and supplies the reactive gas flowing through the gas inlet to the nozzles. Gas channels in the manifold are arranged on a plurality of levels to equalize the lengths of gas paths connecting the gas inlet to each of the plurality of nozzles. This configuration makes the flow rate of reactive gas supplied through each of the plurality of nozzles to the reaction chamber uniform.

Abstract: A method of manufacturing a NOR-type mask ROM device includes forming a first gate electrode for an OFF cell and a second gate electrode for an ON cell on a semiconductor substrate of a first conductivity type. To code the mask ROM device, a plurality of source/drain regions is formed by implanting impurities of a second conductivity type, opposite the first conductivity type, into the semiconductor substrate adjacent only to one side of the first gate electrode and adjacent to both sides of the second gate electrode. To prevent misalignment of a bit line contact hole with a contact region, additional impurities are implanted only into a bit line contact region of the mask ROM device region. When a semiconductor device formed on the same substrate as the mask ROM device includes a double diffused region, additional implantation for both may be realized simultaneously.

Abstract: A capacitor of a memory device, and a method of fabricating the same, includes a lower electrode electrically coupled to a doping region of a transistor structure, the lower electrode having a metal electrode and a metal oxide electrode, a ferroelectric layer covering and extending laterally along the lower electrode, and an upper electrode formed on the ferroelectric layer.

Abstract: A MOS transistor having a T-shaped gate electrode and a method for fabricating the same are provided, wherein the MOS transistor includes a T-shaped gate electrode on a semiconductor substrate; an L-shaped lower spacer disposed at both sides of the gate electrode to cover a top surface of the semiconductor substrate; and low-, mid-, and high-concentration impurity regions formed in the semiconductor substrate of both sides of the gate electrode. The high-concentration impurity region is disposed in the semiconductor substrate next to the lower spacer and the mid-concentration impurity region is disposed between the high- and low-concentration impurity regions. A MOS transistor according to the present invention provides a decrease in a capacitance, a decrease in a channel length, and an increase in a cross-sectional area of the gate electrode. At the same time, the mid-concentration impurity region provides a decrease in a source/drain resistance Rsd.

Abstract: A silicon-oxide-nitride-oxide-silicon (SONOS) memory device includes a memory type transistor including a gate with a SONOS structure on a semiconductor substrate. The gate is formed by sequentially stacking a tunneling oxide layer, a memory node structure including a trap site having nano-sized trap elements in which charges passing through the tunneling oxide layer are trapped, and a gate electrode. The nano-sized trap elements may be a crystal layer composed of nanocrystals that are separated from one another to trap the charges. The memory node structure may include additional memory node layers which are isolated from the nano-sized trap elements.

Abstract: A displacement apparatus for two-dimensional displacement of an object in relation to a fix-point includes a frame that is symmetrical in relation to a center of the frame and adapted to receive first and second actuators, each of which exerts a force along respective first and second axes extending through the center of the frame for deformation of respective first and second specific parts of the frame.

Abstract: In a method of forming a conductive line for a semiconductor device using a carbon nanotube and a semiconductor device manufactured using the method, the method includes activating a surface of an electrode of the semiconductor device using surface pretreatment to create an activated surface of the electrode, forming an insulating layer on the activated surface of the electrode, and forming a contact hole through the insulating layer to expose a portion of the activated surface of the electrode, and supplying a carbon-containing gas onto the activated surface of the electrode through the contact hole to grow a carbon nanotube, which forms the conductive line, on the activated surface of the electrode. Alternatively, the activation step of the surface of the electrode may be replaced with a formation of a catalytic metal layer on the surface of the electrode.

Abstract: In an apparatus and method of noninvasively measuring a concentration of a blood component, the method includes (a) varying a thickness of a body part of a subject, measuring absorption spectrums at different thicknesses of the body part, obtaining a first differential absorption spectrum between the absorption spectrums measured at different thicknesses, actually measuring concentrations of the blood component, and establishing a statistical model using the first differential absorption spectrum and the actually measured concentrations; and (b) estimating the concentration of the blood component using a second differential absorption spectrum obtained with respect to the body part based on the statistical model.

Abstract: An improved method for extrapolating worst-case Simulation Program with Integrated Circuit Emphasis (SPICE) model parameters for an integrated circuit including manufacturing semiconductor devices, measuring typical data and worst-case data with respect to various electrical characteristics of the manufactured devices, determining a set of typical SPICE model parameters using the typical data, and determining a set of worst-case SPICE model parameters using the typical data and the worst-case data. Determining the set of worst-case SPICE model parameters preferably includes extrapolating statistical model parameters using the typical data and the worst-case data and determining the set of worst-case SPICE model parameters using the statistical model parameters.

Abstract: An analyzing method and system includes projecting light onto a specimen, detecting an optical spectrum from the specimen, dividing the detected optical spectrum by a predetermined time interval, applying a weighting vector and a gain and offset vector to the divided spectra to generate a resolution vector, quantizing an analog signal of the resolution vector to a digital signal, and applying a synthesis vector to the quantized spectra to restore the quantized spectra to a size of the optical spectrum. A spectrum having a large amplitude difference is temporally divided and is analyzed by applying different resolutions to individual time intervals. Spectral portions of the spectrum having relatively small peak amplitudes are selected as a region of interest (ROI) to be modified.

Abstract: A method of driving an ink-jet printhead, which heats ink contained in an ink chamber using a heater to generate and expand a bubble within the ink chamber and ejects ink from the ink chamber using an expansive force of the bubble, the method including applying a main pulse to the heater to eject ink and applying a post pulse to the heater after ink has been ejected.

Abstract: In a storage electrode of a semiconductor device, and a method of forming the same, the storage electrode includes an outer cylinder including a first outer cylindrical portion having a first outer diameter, and a second outer cylindrical portion that is formed on the first outer cylindrical portion and having a second outer diameter, which is less than the first outer diameter, the first and second outer cylindrical portions having substantially equal inner diameters, and an inner cylinder formed on inner surfaces of the outer cylinder.

Abstract: A composition for forming a ferroelectric thin film includes: a PZT sol-gel solution including at least one of: a whole or partial hydrolysate of a lead precursor and a whole or partial hydrolyzed and polycondensated product thereof; a whole or partial hydrolysate of a zirconium precursor, a whole or partial hydrolyzed and polycondensated product thereof, and a zirconium complex having at least one hydroxy ion and at least one non-hydrolyzable ligand; and a whole or partial hydrolysate of a titanium precursor, a whole or partial hydrolyzed and polycondensated product thereof, and a titanium complex having at least one hydroxyl ion and at least one non-hydrolyzable ligand; and a Bi2SiO5 sol-gel solution including at least one of: a whole or partial hydrolysate of a silicon precursor and a whole or partial hydrolyzed and polycondensated product thereof, and a resultant obtained by refluxing triphenyl bismuth as a bismuth precursor.

Abstract: An apparatus for cleaning a semiconductor wafer and method for cleaning a wafer using the same wherein, the apparatus includes a chamber on which a wafer is mounted, a revolving chuck mounted in the chamber for supporting and fixing the wafer, a nozzle for spraying cleaning solution onto the wafer, a cover for covering an upper part of the chamber, and a light source. The cleaning solution, preferably one of ozone water, hydrogen water, or electrolytic-ionized water, may be heated for a short time and used to clean the wafer.

Abstract: In a method of aligning a wafer, which is capable of precisely and rapidly aligning the wafer, and a wafer alignment apparatus using the method of aligning the wafer, a first wafer is aligned to form a first template pattern corresponding to an image of the first wafer. Image data of a second wafer is inputted. A kind of the second wafer is different from that of the first wafer. A second template pattern is formed by transforming the first template pattern in response to the image data of the second wafer. The second wafer is then aligned in response to the second template pattern. Accordingly, the template pattern is formed using the image data to align the wafer although wafers having different images are inspected, thereby rapidly forming the template pattern.

Abstract: A semiconductor device and a method of manufacturing the same which yields high reliability and a high manufacturing yield. The semiconductor device includes a metal line layer having a plurality of metal line patterns spaced apart from each other, and at least one underlying layer under the metal line layer, wherein the space between two adjacent metal line patterns has a sufficient width to prevent a crack from occurring in one or more of the underlying layers. The cracking of an underlying layer may also be prevented by providing a slit in a direction parallel to the space between two adjacent metal line patterns at a sufficient distance from the space between the two adjacent metal line patterns.

Abstract: A split gate memory device and fabricating method thereof, wherein gate insulating and polysilicon layers are sequentially formed on a substrate. The polysilicon layer is patterned and a capping insulating layer is formed on portions thereof. A pair of self-aligned control gates having identical bottom widths are formed with a tunnel insulating layer interposed between the control gates and sidewalls of the polysilicon layer pattern and capping insulating layer. The tunnel insulating layer, patterned polysilicon layer and gate insulating layer are selectively etched to expose a portion of the substrate thereby forming a pair of floating gates. Ions are implanted into the exposed substrate and portions of the substrate adjoining the control gates to form a common source region and a drain region, respectively. The capping insulating layer on the floating gate protects an acute section of the tunnel insulating layer from attack during the etching and ion implantation.

Abstract: An air-gap type film bulk acoustic resonator (FBAR) is created by securing two substrate parts, one providing a resonance structure and the other providing a separation structure, i.e., a cavity. When the two substrate parts are secured, the resonance structure is over the cavity, forming an air gap isolating the resonant structure from the support substrate. The FBAR may be used to form a duplexer, which includes a plurality of resonance structures, a corresponding plurality of cavities, and an isolation part formed between the cavities. The separate creation of the resonance structures and the cavities both simplifies processing and allows additional elements to be readily integrated in the cavities.

Abstract: In a method of forming a polysilicon film, a thin film transistor including a polysilicon film, and a method of manufacturing a thin film transistor including a polysilicon film, the thin film transistor includes a substrate, a first heat conduction film on the substrate, a second heat conduction film adjacent to the first heat conduction film, the second heat conduction film having a lower thermal conductivity than the first heat conduction film, a polysilicon film on the second heat conduction film and the first heat conduction film adjacent to the second heat conduction film, and a gate stack on the polysilicon film. The second heat conduction film may either be on the first heat conduction film or, alternatively, the first heat conduction film may be non-contiguous and the second heat conduction film may be interposed between portions of the non-contiguous first heat conduction film.