Abstract: An optical chassis includes a mount substrate an optoelectronic device on the mount substrate, a spacer substrate, and a sealer substrate. The mount substrate, the spacer substrate and the sealer substrate are vertically stacked and hermetically sealing the optoelectronic device. An external electrical contact for the optoelectronic device is provided outside the sealing. At least part of the optical chassis may be made on a wafer level. A passive optical element may be provided on the sealer substrate or on another substrate stacked and secured thereto.

Abstract: An image capturing device (1) is disclosed comprising an electronic image detector (17) having a detecting surface (15), an optical projection system (5) for projecting an object within a field of view onto the detecting surface (15), and, optionally, a computing unit (19) for manipulating electronic information obtained from the image detector (17), wherein, the projection system (5) is adapted to project the object in a distorted way such that, when compared with a standard lens system, the projected image is expanded in a center region of the field of view and is compressed in a border region of the field of view. Preferably, the projection system (5) is adapted such that its point spread function in the border region of the field of view has a full width at half maximum corresponding essentially to the size of corresponding pixels of the image detector (17).

Abstract: A method of forming a mask pattern, a method of forming a minute pattern, and a method of manufacturing a semiconductor device using the same, the method of forming the mask pattern including forming first mask patterns on a substrate; forming first preliminary capping layers on the first mask patterns; irradiating energy to the first preliminary capping patterns to form second preliminary capping layers ionically bonded with the first mask patterns; applying an acid to the second preliminary capping layers to form capping layers; forming a second mask layer between the capping layers, the second mask layer having a solubility lower than that of the capping layers; and removing the capping layers to form second mask patterns.

Abstract: A fuel processor and a fuel cell system which have a desulfurizer with multiple sensors, and a method of measuring an adsorbent state in of an adsorbent the desulfurizer. The desulfurizer determines the saturation state of the adsorbent using a signal difference between at least two sensors installed adjacent to an inlet and an outlet of the desulfurizer. The desulfurizer provides an accurate determination of the saturation of the adsorbent, and can be used to determine when the adsorbent should be changed. Two desulfurizers can be alternatively used to allow for a consistent fuel flow.

Abstract: An interconnection structure and an electronic device employing the same are provided. The interconnection structure for an integrated structure includes first and second contact plugs disposed on a substrate, and a connection pattern interposed between sidewalls of the first and second contact plugs and configured to electrically connect the first and second contact plugs.

Abstract: A direct liquid feed fuel cell stack includes a first end plate and a second end plate facing each other, and a plurality of unit cell modules mounted between the first end plate and the second end plate, wherein an electrical circuit that contacts terminals of the unit cell modules is formed on an inner surface of the first end plate.

Abstract: A mobile System on Chip (SoC) comprises a microprocessor and a first memory controller configured to control a refresh of a first memory. A temperature sensor detects a temperature in the first memory. When first temperature information received from the temperature sensor indicates that the detected temperature deviates from a predetermined temperature range, the first memory controller controls the first memory so as not to perform a self refresh. When second temperature information received from the temperature sensor indicates that the detected temperature is in the predetermined temperature range, the first memory controller outputs a self refresh command to the first memory.

Abstract: A semiconductor memory device may include a parity generating circuit, a memory cell array, an error calculating circuit and an error corrector. The parity generating circuit generates parities having different number of bits according to types of a partial array self-refresh mode, and selects one of the parities to output a first parity. The error calculating circuit calculates an error based on a first data corresponding to the input data and a second parity corresponding to the first parity and outputs a first error data. The error corrector corrects the first data based on the first data and the first error data.

Abstract: A PDP includes a first substrate and a second substrate facing each other, a plurality of first discharge electrodes on the first substrate, a first dielectric layer covering the plurality of first discharge electrodes, and a plurality of second discharge electrodes on the second substrate to cross the plurality of first discharge electrodes, wherein a difference between thermal expansion coefficients of the first substrate and the first dielectric layer is greater than or equal to about 2×10?7/° C. and less than or equal to about 17×10?7/° C.

Abstract: An organic light-emitting display device having a pixel unit to test pixels, wherein the organic light-emitting display device includes: a substrate; a display unit located on the substrate; a plurality of first scan lines located in the display unit; and a second scan line located in the display unit and separated from the first scan lines, wherein a plurality of pixel units, except one test pixel unit located in at least one corner of the display unit, are electrically connected to the first scan lines, and the test pixel unit that is not connected to the first scan lines is electrically connected to the second scan line.

Abstract: A positive active material composition for a rechargeable battery, a positive electrode including the same, and a rechargeable battery including the same, the positive active material composition including a positive active material and a surface-modified metal oxide.

Abstract: A flexible substrate for a TFT includes a metal substrate having a predetermined coefficient of thermal expansion, and a buffer layer on the metal substrate, the buffer layer including a silicon oxide or a silicon nitride, wherein the predetermined coefficient of thermal expansion of the metal substrate satisfies an equation as follows, ? f + 0.162 × ( 1 - v f ) E f ? ? s ? ? f + 0.889 × ( 1 - v f ) E f Ef representing Young's modulus of the buffer layer, vf representing Poisson's ratio of the buffer layer, ?f representing a coefficient of thermal expansion of the buffer layer, and ?s representing the predetermined coefficient of thermal expansion of the metal substrate.

Abstract: A flat panel display apparatus, including a substrate, a display unit disposed on the substrate, a first interconnecting line positioned on the substrate at an outer side of the display unit, a second interconnecting line located above the first interconnecting line, and at least two insulating layers interposed between the first and second interconnecting lines.

Abstract: A semiconductor device includes a lower semiconductor layer with first conductive regions and including at least one dummy first conductive region, an upper semiconductor layer with second conductive regions on the lower semiconductor layer and including at least one dummy second conductive region, a penetration hole in the upper semiconductor layer and penetrating the dummy second conductive region and the upper semiconductor layer under the dummy second conductive region, a lower conductive line on the lower semiconductor layer and electrically connected to the first conductive regions, an upper conductive line on the upper semiconductor layer and electrically connected to the second conductive regions, and a first conductive plug in the penetration hole between the lower conductive line and the upper conductive line, the first conductive plug electrically connecting the lower and upper conductive lines and being spaced apart from sidewalls of the penetration hole.

Abstract: A method for manufacturing a solar cell according to an exemplary embodiment includes: forming a first doping film on a substrate; patterning the first doping film so as to form a first doping film pattern and so as to expose a portion of the substrate; forming a diffusion prevention film on the first doping film pattern so as to cover the exposed portion of the substrate; etching the diffusion prevention film so as to form spacers on lateral surfaces of the first doping film pattern; forming a second doping film on the first doping film pattern so as to cover the spacer and exposed substrate; forming a first doping region on the substrate surface by diffusing an impurity from the first doping film pattern into the substrate; and forming a second doping region on the substrate surface by diffusing an impurity from the second doping film pattern into the substrate.

Abstract: A semiconductor device and a method of fabricating a semiconductor device that includes forming an interlayer insulating film on a semiconductor substrate; depositing a first soft magnetic thin film on the interlayer insulating film through sputtering using a target containing at least one of Fe, Co, Ni, or alloys thereof, the target further containing at least one of Ti, Hf, or B, the sputtering being performed using an N2 reactive gas; forming a metal film on the first soft magnetic thin film; depositing a second soft magnetic thin film on the metal film through sputtering using the same or another target containing at least one of Fe, Co, Ni, or alloys thereof, the target further containing at least one of Ti, Hf, or B, the sputtering being performed using an N2 reactive gas; and patterning to form an inductor.

Abstract: A plasma display apparatus includes a plasma display panel (PDP), a chassis base secured on a first side to the PDP and having a driving circuit board mounted on a second side, a tower-shaped fixing unit that protrudes above the second side of the chassis base, and a back cover secured to a tower unit of the tower-shaped fixing unit to cover the driving circuit board.

Abstract: A SONOS memory device, and a method of manufacturing the same, includes a substrate and a multifunctional device formed on the substrate. The multifunctional device performs both switching and data storing functions. The multifunctional device includes first and second impurities areas, a channel formed between the first and second impurities areas, and a stacked material formed on the channel for data storage. The stacked material for data storage is formed by sequentially stacking a tunneling oxide layer, a memory node layer in which data is stored, a blocking layer, and an electrode layer.

Abstract: A lead plate for connecting a printed circuit board (PCB) of a secondary battery to an bare cell includes a mounting portion connected to the PCB, a joint portion connected to the bare cell, a surface area of the joint portion facing the bare cell being smaller than a surface area of the mounting portion facing the PCB, and a step portion connecting the mounting portion and the joint portion to each other.

Abstract: A battery pack includes a battery including a positive electrode and a negative electrode, a switching module including a charge switching device and a discharge switching device, the charge switching device and discharge switching device being electrically connected to a high current path of the battery, a battery management unit (BMU) electrically connected to the switching module, the BMU being configured to adjust a limit value for a charging current supplied by the charge switching device and to set a magnitude of the charging current supplied by the charge switching device to be equal to or less than the adjusted.