Abstract: An array of solder structures comprising a plurality of radially-curved exterior surfaces, each one enclosing a predetermined-sized cavity that can be used for flexibly joining together at predetermined conductive contact points two planar elements having dissimilar properties. By assembling the two planar elements in a tiered arrangement, one planar element having an array of annular conductive pads and the other planar element having either a corresponding array of annular or circular conductive pads, separated by an array of spherical solder balls comprised of solder and a fluxing agent, a hollow solder structure can be created during a melting and subsequent cooling of the solder compound. The plasticity/resiliency characteristics of the resulting hollow solder structure absorbs lateral movement of the two planar elements relative to each other without degradation of the solder joint.

Abstract: A high-capacitance capacitor having a multi-layered vertical structure for use in an RF circuit is disclosed. The capacitor includes an upper electrode, a lower electrode, and a dielectric layer interposed between the two electrodes. A plurality of electrodes is formed in parallel in the dielectric layer in a diagonal direction. First electrodes, which are half of the plurality of electrodes, are coupled to only the upper electrode, while second electrodes, which are the other half of the plurality of electrodes, are coupled to only the lower electrode. The first electrodes and the second electrodes are alternately positioned in rows and columns. The capacitor does not require additional processes, thereby reducing complexity and cost of fabrication thereof.

Abstract: A method for manufacturing a capping layer covering a capacitor of a semiconductor memory device, preferably a metal-insulator-metal (MIM) capacitor, wherein the method includes forming a capacitor having a lower electrode, a dielectric layer and an upper electrode on a semiconductor substrate, forming a capping layer on the capacitor, and crystallizing the dielectric layer. Here, forming the capping layer includes stabilizing for deposition of the capping layer without providing oxygen gas, depositing the capping layer by providing a reaction source for the capping layer; and purging an inside of a reactor for forming the capping layer.

Abstract: A ferroelectric multi-layered emitter used in a semiconductor lithography process includes a lower electrode, a ferroelectric layer, having a top surface with two end portions, which overlies the lower electrode, an insertion electrode formed on a region excluding the two end portions of the top surface of the ferroelectric layer, a dielectric layer, having sides and a top surface with two end portions, which has a predetermined pattern and is formed along the top surface of the ferroelectric layer and the insertion electrode, and a dummy upper electrode formed on a side of the dielectric layer opposite the ferroelectric layer. The ferroelectric emitter of the present invention guarantees uniform electron emission from wide and narrow gaps of a mask layer and in an isolated pattern such as a doughnut shape for ferroelectric switching emission lithography.

Abstract: A substrate bias generator which makes device characteristics stable by supplying a predetermined negative voltage to a substrate and minimally reduces current consumption during a self refresh mode. The substrate bias generator comprises a substrate voltage level detector for inputting a substrate voltage and outputting a signal which drives an oscillator in response to the input level, and a controller for inputting a chip active enable signal, a self refresh mode enable signal and an output signal of the substrate voltage level detector and controlling a switching operation of the substrate voltage level detector in response to the input level.

Abstract: A cathode active material and a lithium secondary battery employing the same are provided.

Abstract: In a structure of a radio frequency (RF) variable capacitor having a variable range of capacitance between a first minimum value and a first maximum value, and a method of manufacturing the structure, the structure includes a first capacitor, which has a variable range of capacitance between a second minimum value greater than the first minimum value and a second maximum value greater than the first maximum value, and a second capacitor, which is connected in series to the first capacitor and has a capacitance of a fixed value. By the structure and method, a quality factor of a radio frequency (RF) variable capacitor may be increased without adding complex processing steps.

Abstract: An image sensor device and method for forming the same include a photodiode formed in a substrate, at least one electrical interconnection line electrically associated with the photodiode, a light passageway having a light inlet, the light passageway being positioned in alignment with the photodiode, a color filter positioned over the light inlet of the light passageway and a lens positioned over the color filter in alignment with the light passageway wherein the at least one electrical interconnection line includes a copper interconnection formation having a plurality of interlayer dielectric layers in a stacked configuration with a diffusion barrier layer between adjacent interlayer dielectric layers, and a barrier metal layer between the copper interconnection formation and the plurality of interlayer dielectric layers and intervening diffusion barrier layers. An image sensor device may employ copper interconnections if a barrier metal layer is removed from above a photodiode.

Abstract: A blue electroluminescent polymer comprising diphenylanthracene units in a main chain of polymer and an organic electroluminescence device using the blue electroluminescent polymer, to provide improved luminescent properties.

Abstract: A photo-alignment material useful in liquid crystal alignment films comprises a maleimide-based repeating unit, or a maleimide-based repeating unit and at least one additional repeating unit. The photo-alignment materials of the invention may be used in liquid crystal display devices to improve the electrical and electrooptical properties of the alignment film, and thereby improve the reliability of products using the alignment films.

Abstract: A nonvolatile memory device and a method of forming the nonvolatile memory device having a shallow trench isolation structure and having a device isolation layer having a protruding portion above a substrate surface includes forming a gate oxide, a lower conductive layer pattern, and a hard mask layer; patterning the hard mask layer; isotropically etching the lower conductive layer to form a lower conductive layer pattern having a sloped sidewall profile where a width of a lower portion of the lower conductive layer pattern is smaller than a width of an upper portion of the lower conductive layer pattern; etching the gate oxide layer and the substrate, using the hard mask pattern as an etch mask, to form a trench; and forming a device isolation layer contacting with a sidewall of the lower conductive layer pattern in the trench.

Abstract: The present invention provide a vertical nano-sized transistor using carbon nanotubes capable of achieving high-density integration, that is, tera-bit scale integration, and a manufacturing method thereof, wherein in the vertical nano-sized transistor using carbon nanotubes, holes having diameters of several nanometers are formed in an insulating layer and are spaced at intervals of several nanometers. Carbon nanotubes are vertically aligned in the nano-sized holes by chemical vapor deposition, electrophoresis or mechanical compression to be used as channels. A gate is formed in the vicinity of the carbon nanotubes using an ordinary semiconductor manufacturing method, and then a source and a drain are formed at lower and upper parts of each of the carbon nanotubes thereby fabricating the vertical nano-sized transistor having an electrically switching characteristic.

Abstract: A CMOS semiconductor device and a method of manufacturing the same in which the gate induced drain leakage (GIDL) effect is reduced. In the semiconductor device of this invention, high concentration source/drain regions of a PMOS transistor are formed away from the gate pattern sidewall spacers. This is accomplished by using as an implant mask a dielectric film formed on an entire surface of a semiconductor substrate, where the semiconductor substrate includes a PMOS transistor region in an n-well, a low concentration source/drain regions of a PMOS transistor formed by using a gate pattern as an implant mask, the PMOS transistor gate pattern sidewall spacers, and an NMOS transistor region in a p-well with the NMOS transistor having both a low concentration and a high concentration source/drain regions.

Abstract: A magnetic memory device includes a memory cell array block and a reference memory cell array block having a plurality of magnetic memory cells arranged, respectively, at intersections of wordlines, digit lines, and bitlines, and reference wordlines, the digit lines, and a reference bitline, a first bitline clamp circuit coupled to a bitline to which a first selected magnetic memory cell is connected and supplying a first current to the first selected magnetic memory cell through the bitline, second and third bitline clamp circuits coupled to respective upper and lower ends of the reference bitline, for supplying a second current to selected magnetic memory cells in the reference memory cell array block through the reference bitline, and a sense amplifier for sensing and amplifying currents on first and second data lines, respectively connected to the bitline and the reference bitline, to judge data of the first selected magnetic memory cell.

Abstract: A method for forming a storage node contact plug of a dynamic random access memory includes forming insulating layers on an overall surface of a semiconductor substrate having a plurality of buried contact plugs, etching the insulating layers down to a top surface of the buried contact plugs to form first contact holes on the buried contact plugs, forming a photoresist pattern on the insulating layers and the first contact holes, etching the insulating layers to form second contact holes on the second insulating layer, and filling the first and second contact holes with conductive material.

Abstract: A trench isolation in a semiconductor device, and a method for fabricating the same, includes: forming a trench having inner sidewalls for device isolation in a silicon substrate; forming an oxide layer on a surface of the silicon substrate that forms the inner sidewalls of the trench; supplying healing elements to the silicon substrate to remove dangling bonds; and filling the trench with a device isolation layer, thereby forming the trench isolation without dangling bonds causing electrical charge traps.

Abstract: An apparatus for polishing a wafer includes a polishing station having a platen on which a polishing pad is installed, a polishing head having a membrane that contacts a surface of the wafer, the membrane securing the wafer and pressuring the wafer against the polishing pad, wherein the polishing station includes a transfer stage for loading the wafer on or unloading the wafer from the polishing head, and wherein the transfer stage includes a pedestal on which the wafer is placed and a fluid supply part for supplying a fluid into a boundary region between the wafer and the membrane to reduce a surface tension between the wafer and the membrane. Preferably, the apparatus further includes a stopper for preventing the wafer placed on the pedestal from being lifted up along with the membrane when the wafer is unloaded from the polishing head onto the pedestal.

Abstract: A blue electroluminescent polymer comprising biphenyl units in a main chain of polyarylene, and an organic electroluminescence device using the blue electroluminescent polymer to provide improved luminescent properties.

Abstract: An apparatus for acquisition of an asynchronous wideband direct-sequence/code division multiple access signal, which acquires a long code from a direct-sequence/code division multiple access control channel signal, in which a common short code, and the long code are transmitted within one frame, and a group identification code indicating a code group, to which a base station belongs, are combined and transmitted with the common short code, includes: a long code masking correlation portion; a differentially coherent combining portion; a code group and frame timing acquisition portion; and a long code acquisition portion for acquiring the long code by correlating the long codes belonging to the acquired code group and the received long code, respectively.

Abstract: A semiconductor device and a method for manufacturing the same, wherein a gate electrode structure is formed on a surface of a semiconductor substrate. Next, a gate poly oxide (GPOX) layer is deposited on a surface of the gate electrode structure and on the semiconductor substrate. Then, the surface of the semiconductor substrate is cleaned to remove any residue and the GPOX layer remaining on the semiconductor substrate. Next, an etch stopper is formed on the surface of the gate electrode structure and on the semiconductor substrate. Last, a high-density plasma (HDP) oxide layer is deposited on the etch stopper. The semiconductor device and method for manufacturing the same are capable of preventing bubble defects.