Abstract: A wet-pipe sprinkler system, method of supplying water to the system, and method of dealing with a leakage of the system are provided, wherein the wet-pipe sprinkler system includes a sprinkler head; a plurality of interconnected pipes for supplying water to the sprinkler head; at least one water supply connected to one end of the pipes; an electric main valve for controlling inflow of water to the pipes; an electric drain valve to drain water from the pipes; a first electrical control circuit in a central control studio which outputs a drain valve opening signal to the electric drain valve and a main valve closing signal to the electric main valve when a leakage is detected, thereby blocking the water from entering the pipes and draining the water from the pipes. Accordingly, a leak may be dealt with promptly, thereby minimizing damage caused by the leakage.

Abstract: A furnace temperature detector includes a spike thermocouple attached to a heating chamber; an overheat thermocouple attached to the heating chamber; an inner thermocouple installed inside a reaction tube; a temperature controller connected to the spike thermocouple and the inner thermocouple; an overheat controller connected the overheat thermocouple; and a control switch for directing the output line of the overheat thermocouple. When the furnace overheats, the overheat thermocouple detects the overheating and generates and outputs an electric signal corresponding to the overheating to the overheat controller; the overheat controller generates and outputs an overheat control signal.

Abstract: A composition for an anti-reflective layer capable of simultaneously being developed together with a photoresist layer after exposure of the photoresist layer in a photolithography process and a method for forming patterns in a semiconductor device using the composition, wherein the anti-reflective light absorbing layer composition includes a polymer having a (meth)acrylate repeating unit, a light-absorbing group of diazoquinones chemically bound to the (meth)acrylate repeating unit, a photoacid generator, a cross-linker which thermally cross-links the polymer and is decomposed from the polymer by an acid, and a catalyst for the cross-linking reaction of the polymer. The method for forming patterns in a semiconductor device involves forming an anti-reflective layer on a semiconductor substrate using the composition and simultaneously exposing the anti-reflective layer and a photoresist layer, thereby chemically transforming the anti-reflective layer so it is able to be developed.

Abstract: A method of forming a contact hole of a semiconductor device that is able to prevent excessive etching of an interlayer dielectric pattern includes forming a gate pattern including a first insulation layer pattern, a conductive layer pattern, a capping insulation layer pattern, and a second insulation layer pattern on a substrate; forming a spacer using an insulating material on a sidewall of the gate pattern; forming an interlayer dielectric on the substrate on which the gate pattern and the spacer are formed; forming a contact hole and an interlayer dielectric pattern for exposing the substrate by etching the interlayer dielectric; forming a liner spacer on a sidewall of the spacer and the interlayer dielectric pattern; and cleaning the resultant structure using a cleaning solution. The cleaning solution preferably includes includes ozone water and hydrogen fluoride (HF).

Abstract: A memory device having one transistor and one resistant element as a storing means and a method for driving the memory device, includes an NPN-type transistor formed on a semiconductor substrate, an interlayer insulating film formed on the semiconductor substrate to cover the transistor in which a contact hole exposing a source region of the transistor is formed, a resistant material in which a bit data “0” or “1” is written connected to the source region of the transistor by a conductive plug or an insulating film, and a conductive plate contacting the resistant material. The memory device exhibits improved degree of integration, reduced current consumption by lengthening a refresh period thereof, and enjoys simplified manufacturing process due to a simple memory cell structure.

Abstract: An information processing system for controlling clock skew preferably includes a first and a second memory module, each of which has at last one semiconductor integrated circuit and is controlled by a chipset which can selectively control the time delay of an individual clock signal based on a stored value. The system further includes a clock line, which includes a first and a second clock line segment forming a closed loop and at least one data line connected between the chipset and a first termination device. By designing each of the first and the second clock line segments to be the same length as the data line, the propagation time of a clock signal and a data signal may be accurately matched.

Abstract: A trench isolation in a semiconductor device, and a method for fabricating the same, includes: forming a trench having inner sidewalls for device isolation in a silicon substrate; forming an oxide layer on a surface of the silicon substrate that forms the inner sidewalls of the trench; supplying healing elements to the silicon substrate to remove dangling bonds; and filling the trench with a device isolation layer, thereby forming the trench isolation without dangling bonds causing electrical charge traps.

Abstract: A metal wiring method for an undercut in a MEMS packaging process includes disposing a MEMS element on a silicon substrate, welding a glass wafer to an upper portion of the silicon substrate having the MEMS element disposed thereon, the glass wafer having a hole formed therein for connecting a metal wiring, depositing a thin metal film for the metal wiring in the hole, and ion-mealing the deposited thin metal film. By the ion-mealing, the method is capable of connecting a metal wiring to a via hole having an undercut.

Abstract: A polymer having a repeating unit comprising a copolymer of butadiene sulfone and maleic anhydride, and a chemically amplified resist composition comprising the polymer. The resist composition includes a photosensitive polymer having a first repeating unit comprising a copolymer of butadiene sulfone and maleic anhydride, the first repeating unit represented by a formula: and a second repeating unit copolymerized with the first repeating unit.

Abstract: An inductively coupled plasma apparatus is provided, wherein the inductively coupled plasma apparatus includes a process chamber having a wafer susceptor on which a substrate is installed, a top plasma source chamber which is installed on the process chamber, a reactor, which is installed in the top plasma source chamber, having a channel through which a gas flows, wherein the reactor supplies plasma reaction products to the process chamber, an inductor, having two ends, is installed between the top plasma source chamber and the reactor and is wound around the reactor, an opening which is positioned within a circumferential space in which the inductor is installed between the reactor and the process chamber, and a shutter operable to open and close the opening. Thus, a uniform radial distribution of radicals emanating from a plasma source can be improved.

Abstract: A method for forming a lithium anode protective layer comprises activating the surface of the lithium metal anode and forming a LiF protective layer on the activated surface of the lithium metal anode.

Abstract: An apparatus for improving the density and uniformity of plasma in the manufacture of a semiconductor device features a plasma chamber having a complex geometry that causes plasma density to be increased at the periphery or edge of a semiconductor wafer being processed, thereby compensating for a plasma density that is typically more concentrated at the center of the semiconductor wafer. By mounting a target semiconductor wafer in a chamber region that has a cross-sectional area that is smaller than a cross-sectional area of a plasma source chamber region, a predetermine flow of generated plasma from the source becomes concentrated as it moves toward the semiconductor wafer, particularly at the periphery of the semiconductor wafer. This provides a more uniform plasma density across the entire surface of the target semiconductor wafer than has heretofore been available.

Abstract: The present invention provide a vertical nano-sized transistor using carbon nanotubes capable of achieving high-density integration, that is, tera-bit scale integration, and a manufacturing method thereof, wherein in the vertical nano-sized transistor using carbon nanotubes, holes having diameters of several nanometers are formed in an insulating layer and are spaced at intervals of several nanometers. Carbon nanotubes are vertically aligned in the nano-sized holes by chemical vapor deposition, electrophoresis or mechanical compression to be used as channels. A gate is formed in the vicinity of the carbon nanotubes using an ordinary semiconductor manufacturing method, and then a source and a drain are formed at lower and upper parts of each of the carbon nanotubes thereby fabricating the vertical nano-sized transistor having an electrically switching characteristic.

Abstract: A metal gasket for a semiconductor fabrication chamber capable of preventing base plate metal contamination in the chamber, wherein the metal gasket includes a diffusion barrier layer interposed between a base plate and an anti-corrosive coating layer, and wherein the diffusion barrier layer prevents elements of the base plate from being diffused to the anti-corrosive coating layer. Accordingly, the diffusion barrier layer prevents attack on the anti-corrosive coating layer.

Abstract: A semiconductor device having a thin film formed by atomic layer deposition and a method for fabricating the same, wherein the semiconductor device includes a liner layer formed on an internal wall and bottom of a trench, gate spacers formed on the sidewalls of gate stack patterns functioning as a gate line, a first bubble prevention layer formed on the gate spacers and the gate stack patterns, bit line spacers formed on the sidewalls of bit line stack patterns functioning as a bit line, and a second bubble prevention layer formed on the bit line spacers and the gate stack patterns and at least one of the above is formed of a multi-layer of a silicon nitride layer and a silicon oxide layer, or a multi-layer of a silicon oxide layer and a silicon nitride layer, thereby filling the trench, gate stack patterns, or bit line stack patterns without a void.

Abstract: In a semiconductor memory device, a circuit for controlling a voltage level applied to a bit line isolation circuit preferably includes a memory cell connected between a cell bit line pair and a word line; a bit line pre-charge circuit; a sense amplifier bit line pre-charge circuit; a charge transfer circuit connected between the cell bit line pair and the sense amplifier bit line pair; a first sense amplifier circuit for amplifying a voltage of the sense amplifier bit line pair to a first voltage in response to a first control signal; and a second sense amplifier circuit for amplifying the voltage of the sense amplifier bit line pair to a second voltage in response to a second control signal. The combination of the two-stage sense amplifier ciruitry allows for the accurate determination of minimally-different logical voltage levels and minimized circuit area.

Abstract: A method for fabricating a capacitor of a semiconductor device, and a capacitor made in accordance with the method, wherein the method includes forming a plate electrode polysilicon layer on a semiconductor substrate having a cell array region and a core/peripheral circuit region. The plate electrode polysilicon layer in the cell array region is patterned to form an opening, wherein the inner wall of the opening is used as a plate electrode. After forming a dielectric layer in the opening, a storage node is formed as a spacer on the dielectric layer on the inner wall of the opening. The plate electrode polysilicon layer in the core/peripheral circuit region remains to provide the same height between the cell array region where the cell capacitor is formed and the core/peripheral circuit region.

Abstract: A plasma enhanced chemical vapor deposition apparatus and a method of forming a nitride layer using the same, wherein the plasma enhanced CVD apparatus includes a process chamber including an upper chamber with a dome shape, a lower chamber, and an insulator therebetween, a gas distributing ring, a susceptor for supporting a wafer and heating the process chamber, a plasma compensation ring surrounding the susceptor, a vacuum pump and an electric power source connected to the process chamber. The gas distributing ring has a plurality of upwardly inclined nozzles, allowing upward distribution of reactive gases. The method of forming a nitride layer includes forming a protective film on inner walls of a process chamber, the protective film having at least two layers of differeing dielectric constant, and sequentially supplying reactive gases to the process chamber. A nitride layer formed thereby has low hydrogen content, good density and oxidation resistance.

Abstract: A method of manufacturing a capacitor having increased capacitance using a single photo-lithographic step to form two holes of different sizes in the insulating layers, wherein a first insulating layer, an etching stop layer, and a second insulating layer are sequentially deposited on a semiconductor substrate, a preliminary hole is formed by etching a predetermined portion of the second insulating layer, the preliminary hole is expanded so as to form a first hole, a second hole is formed extending from the bottom of the first hole and having an etched area narrower than an etched area of the first hole, a first conductive layer pattern is formed on the sidewalls of the first and second holes and at the bottom surface of the second hole without burying the second hole, thereby increasing the storage capacitance of the capacitor while simplifying the manufacturing process.

Abstract: A semiconductor memory device and a method of manufacturing same, wherein landing pads are formed to contact source/drain regions of an access transistor in a memory cell array area and a first resistor device is formed in the peripheral circuit area, by depositing a first conductive layer on a semiconductor substrate having an access transistor formed thereon and patterning the first conductive layer. An interlayer insulation layer is deposited on the resultant structure, and a lower electrode and a dielectric layer having a high dielectric constant of a capacitor are formed to contact the source/drain region of the access transistor. By depositing a second conductive layer on the resultant structure having the dielectric layer and patterning the dielectric layer, a capacitor upper electrode is formed in the memory cell array area and a second resistor device is formed in the peripheral circuit area.