Abstract: A method of monitoring contact holes of an integrated circuit using corona charges is provided for determining whether the contact holes are open. The method includes transmitting corona charges over a unit chip having contact holes on a semiconductor wafer; measuring the surface voltage of the unit chip; making a graph illustrating a relationship between the amount of corona charges transmitted and the measured surface voltage of the unit chip; and analyzing the graph to determine whether the contact holes of the unit chip are open. According to the method of the present invention, contact holes may be monitored at an in-line state when manufacturing an integrated circuit by transmitting corona charges onto a unit chip, eliminating the need to use a scanning electronic microscope, thereby preventing a reduction in yield.

Abstract: A method of cleaning damaged layers and polymer residue on semiconductor devices includes mixing HF and ozone water in a vessel to form a solution of HF and ozone water, and dipping a semiconductor device in the vessel containing the solution of HF and ozone water. Preferably, ozone water is subsequently introduced into the vessel to replace the solution of HF and ozone water in the vessel.

Abstract: In a method for forming a semiconductor device and a semiconductor device having an overlay mark, a first pattern for the semiconductor device is formed in a semiconductor device formation region of a semiconductor substrate and simultaneously in a first mark formation region of the semiconductor substrate. A second pattern for the semiconductor device is formed on a resultant structure in the semiconductor device formation region of the semiconductor substrate and simultaneously in a second mark formation region of the semiconductor substrate. The first and second patterns in the first and second mark formation regions, respectively, are inspected for misalignments using overlay marks formed to have shapes and sizes identical to those of real patterns in the semiconductor device formation region of the semiconductor substrate. By measuring misalignments of real patterns using the overlay marks, overlay mismatch between the semiconductor device formation region and the overlay mark may be prevented.

Abstract: An apparatus and method for despreading a CDMA signal, wherein the apparatus performs a predetermined operation on a received CDMA signal and first and second codes to extract a pilot symbol and a data symbol from the received CDMA signal when the first and second codes are generated internally; and includes a correlation unit for performing operations on the respective inphase and quadrature components of the first code and accumulatively storing the results of the operations depending on first and second selection signals obtained from the first and second codes, a decimator for outputting individual accumulated values after individual results of the operation are separately accumulated a predetermined number of times by the correlation unit, and a symbol output unit for performing a predetermined operation on individual values output from the decimator to output the pilot symbol and the data symbol.

Abstract: A method for monitoring an ion implanter includes positioning a substrate behind an interceptor for intercepting a portion of an ion beam to be irradiated toward the substrate, irradiating a first ion beam toward the substrate to form a first shadow on the substrate, rotating the substrate about a central axis of the substrate, irradiating a second ion beam toward the substrate to form a second shadow on the substrate, and measuring a dosage of ions implanted into the substrate to monitor whether the rotation of the substrate has been normally performed. Preferably, a dosage of ions implanted into the substrate is calculated from a thermal wave value of the substrate and whether the rotation of the substrate has been normally performed is monitored by comparing the thermal wave value corresponding to the first shadow with a reference thermal wave value.

Abstract: A process chamber used in the manufacture of a semiconductor device for etching a material layer on a semiconductor wafer includes an electrostatic chuck for holding the semiconductor wafer, and an annular edge ring which surrounds the side of the semiconductor wafer on the electrostatic chuck to prevent the semiconductor wafer from departing from its original position. The annular edge ring has a first side which faces the side of the semiconductor wafer and contacts firmly with the side of the semiconductor wafer.

Abstract: A method for preventing void formation in a polycide structure includes sequentially depositing a gate oxide film, a polysilicon film doped with impurities, a seed film having a sufficient amount of silicon for reacting with an overlaying tungsten layer, a tungsten silicide precursor layer; and an etch mask made of an insulating material on a semiconductor substrate; performing a patterned etching using the etch mask; and heat-treating the resulting structure in an oxygen atmosphere at an elevated temperature and pressure to form a polycide structure wherein void formation is prevented. Since the seed film has a sufficient amount of amorphous silicon for reacting to the tungsten, migration of silicon atoms to the interfacial surface between the polysilicon film and the tungsten silicide precursor layer is prevented, thereby preventing the formation of voids in the polysilicon film.

Abstract: A method of fabricating a capacitor of a semiconductor device, includes forming a lower electrode on a semiconductor substrate, sequentially forming an aluminum oxide layer and a titanium oxide layer on the lower electrode, and forming an upper electrode on the titanium oxide layer, wherein the upper electrode crosses over the lower electrode. The titanium oxide layer is formed to have a thickness in a range of from about 2 Å to about 50 Å, and the upper electrode is formed at a temperature in a range of from about 150° C. to about 630° C. The temperature at which the upper electrode is formed is decreased as the thickness of the titanium oxide layer is increased to produce a capacitor of a semiconductor device having a minimized leakage current characteristic.

Abstract: A rotation-type decoupled MEMS gyroscope including a drive body movable about the X-axis, a sensing body movable about the Z-axis, a medium body moving together with the drive body about the X-axis and the sensing body about the Z-axis. The drive body is fixed on a substrate by a first torsion spring torsion-deformed about the X-axis, and the medium body is connected to the drive body by a first bending spring bending-deformed about the Z-axis. The sensing body is connected to the medium body by a second torsion spring torsion-deformed about the X-axis and fixed to the substrate by a second bending spring bending-deformed about the Z-axis. If angular velocity is applied relative to the Y-axis while the drive body vibrates in a certain range about the X-axis by a driving electrode, the sensing body rotates about the Z-axis by the Coriolis force and a sensing electrode senses the rotation.

Abstract: Acquisition of initial code synchronization in a receiving system for a code division multiple access (CDMA) signal is realized by producing a complex digital signal having K components by sampling an analog signal derived from the received CDMA-modulated signal. Components of the complex digital signal are correlated with N code phases. The energies of these correlated values are examined, in parallel, to determine whether the ratio of the maximum energy within the block to the average energy in the block equals or exceeds a predetermined threshold. If so, this is a valid maximum, and the code synchronization is complete. If not, further components of the complex digital signal are correlated with another set of N code phases, and are examined in the same manner. Accordingly, reliable determination as to whether code synchronization has been achieved can be realized with minimal influence of channel distortion in a CDMA received signal.

Abstract: A wafer stage including an electrostatic chuck and a method for dechucking a wafer using the wafer stage are provided, wherein, the wafer stage includes an electrostatic chuck support, an electrostatic chuck, a lifting means, and a grounding means including a device for connecting the interconnections for grounding the lifting means. According to the method for dechucking a wafer, when a lifting means is in contact with a rear side of the wafer, the lifting means is grounded. Then, an electrostatic chuck is neutralized by supplying power to electrostatic electrodes, and the wafer is neutralized by supplying plasma to the wafer.

Abstract: A method and an apparatus for precisely exposing a predetermined width of a peripheral area of a wafer coated with a layer of photoresist material with light from a light source, wherein the wafer is moved when the light is radiated onto the wafer to expose the photoresist layer at the peripheral area of the wafer, an inspection section inspecting whether the light is radiated onto a precise position of the peripheral area of the wafer, whereby by adjusting the position of the light source if the light is not radiated at the precise position of the peripheral area of the wafer requiring exposure while inspecting the light radiated onto the peripheral area of the wafer, the predetermined width of the peripheral area of the wafer is precisely exposed.

Abstract: An electron emission lithography apparatus and method using a selectively grown carbon nanotube as an electron emission source, wherein the electron emission lithography apparatus includes an electron emission source installed within a chamber and a stage, which is separated from the electron emission source by a predetermined distance and on which a sample is mounted, and wherein the electron emission source is a carbon nanotube having electron emission power. Since a carbon nanotube is used as an electron emission source, a lithography process can be performed with a precise critical dimension that prevents a deviation from occurring between the center of a substrate and the edge thereof and may realize a high throughput.

Abstract: A method of inhibiting pit occurrence on a semiconductor substrate during manufacture of a semiconductor device includes forming an isolation using a shallow trench isolation (STI) method in a semiconductor substrate, forming an insulation layer on an entire surface of the semiconductor substrate having the isolation, implanting ions into the semiconductor substrate using the insulation layer as a buffer layer, annealing the semiconductor substrate using a rapid thermal annealing (RTA) process, forming a photoresist layer on the insulation layer and then forming an opening in the photoresist layer to expose an underlayer thereof, forming an align key by etching the underlayer at the opening, and removing the photoresist layer and the insulation layer. Alternatively, the thickness of the insulation layer may be reduced to prevent the occurrence of pits on active areas of the semiconductor substrate.

Abstract: The present invention provides a temperature-compensating reference voltage generator, including a temperature-compensating voltage divider, or variable voltage generator, for dividing an input reference voltage in order to generate a temperature-compensated output voltage. Preferably included, are a first differential amplifier for amplifying a voltage difference between a first reference voltage and a first feedback voltage in order to output an internal reference voltage, a first voltage divider for generating and outputting a first feedback voltage in response to the temperature-compensated voltage, the first voltage divider further including, two resistive elements for controlling a magnitude of reference voltage.

Abstract: A method of fabricating a semiconductor device having a recess region in an insulation layer on a silicon substrate, comprising the steps of depositing a barrier metal over the entire surface of the insulation layer including the substrate surface in the recess region, depositing selectively an anti-nucleation layer on the barrier metal except in the recess region, depositing a CVD-Al layer on the barrier metal in the recess region, depositing a metal or a metal alloy inhibiting aluminum migration on the anti-nucleation layer and the barrier metal except in the recess region, and depositing a PVD-Al layer and re-flowing the PVD-Al layer, for improving the quality of aluminum grooves. The present method inhibits PVD-Al migration and grain growth, which results in preventing abnormal patterning in the semiconductor device.

Abstract: A pneumatic valve includes a cylinder having at least one gas port for providing inflow and outflow of a gas; a piston arranged in the cylinder and performing a reciprocating, straight-line movement in response to the inflow and outflow of the gas; a first valve shaft passing through the piston and having a first end portion including a first coupling portion; and a second valve shaft including a second coupling portion and having a first end portion protruding from the cylinder, wherein the second coupling portion is coupled to the first coupling portion.

Abstract: A semiconductor package including a double-faced semiconductor chip having integrated circuitry on both sides thereof, and a method of fabricating the same is provided, wherein the semiconductor package includes the semiconductor chip; a lead-on-chip (LOC)-type substrate, having metal patterns on both sides, bonded with the first side of the semiconductor chip; first wires for connecting the first side of the semiconductor chip to the second side of the LOC-type substrate; second wires for connecting the second side of the semiconductor chip to the first side of the LOC-type substrate; a first sealing material for covering the semiconductor chip, the first wires, and the second side of the LOC-type substrate; a second sealing material for covering the semiconductor chip, the second wires, and the first side of the LOC-type substrate; and solder balls attached to the second side of the LOC-type substrate.

Abstract: A transmittance adjustment mask includes a plurality of features and dummy features that correspond to circuit elements of integrated circuits, and uses an exposure device to optically transcribe a pattern corresponding to the integrated circuits onto a semiconductor substrate. The features have predetermined minimum dimensions and include an isolated edge and a plurality of dense edges. The dummy features are spaced apart and parallel from a corresponding isolated edge by a predetermined distance such that a light intensity in the dense edges and the isolated edges of the plurality of features are about the same. The dummy features adjust the amount of light radiated to peripheral areas of the isolated edges to match that radiated to peripheral areas of the dense edges, thereby reducing the difference of dimensions between densely packed features and isolated features transcribed onto the semiconductor substrate.

Abstract: A semiconductor contact structure for a merged dynamic random access memory and a logic circuit (MDL) and a method of manufacturing the contact structure to: (i) a cell contact pad; (ii) at least one active region; and (iii) at least one gate electrode simultaneously, whereby an electric short between the gate electrodes and the cell contact pad is avoided, even in the event a lithographic misalignment occurs and whereby it is possible to obtain an overlap margin in the cell region, even with an improved metal contact to the gate electrode in the peripheral circuit region of the semiconductor device.