Abstract: An electroluminescnet polymer is represented by the following formula (1): wherein X1 to X5 are independently a hydrogen atom, a linear alkyl or alkoxy group having 1 to 40 carbon atoms, a branched alkyl or alkoxy group having 3 to 40 carbon atoms, a cyclic alkyl group having 5 to 40 carbon atoms, a silyl group, or an aromatic group having 6 to 14 carbon atoms which is unsubstituted or substituted with at least one selected from the group consisting of an alkoxy group having 1 to 40 carbon atoms and an amine group.

Abstract: A semiconductor wafer overlay correction method for an exposure process in a semiconductor fabricating stepper incorporates variations in equipment characteristics with time. The wafer overlay correction method includes measuring an overlay error correction value of a semiconductor wafer that is exposed by the stepper, calculating an overlay error correction value by summing the measured overlay error correction value, a variation in the stepper characteristics that is obtained through an empirical characterization of input changes, and a weighting value obtained from a predetermined plurality of wafer lots, and providing the calculated overlay error correction value to the semiconductor fabricating stepper to control an exposure process of a subsequent wafer lot.

Abstract: An improved bumped chip carrier (BCC) package according to the present invention includes a resin-molded lead frame encapsulating an attached semiconductor integrated circuit (IC) and a plurality of interconnecting wire bonds attaching a plurality of contact pads on the IC to an associated plurality of solder-covered external contact terminals that are integrated in the lead frame. By integrally processing the external contact terminals, bonding wires may be affixed using a single wire bonding process. A method for manufacturing the BCC package preferably includes a dual photoresist patterning process accompanied by a dual wet etching process to create a plurality of highly reliable external contact terminals having improved bonding between the contact terminals and the encapsulating resin mold.

Abstract: An apparatus and method for cleaning debris and residue from a multitude of electrical contacts of a test probe card of an integrated circuit test probe apparatus preferably comprises a silicon wafer having a grooved surface into which the test probe card is moved into pressurized contact. The grooved surface provides a grating structure that when combined with the pressurized electrical contacts will crush any intervening or attached residue particles, which will then break into smaller particles and fall away from the probe card. Pressure and relative movement of the probe card may be controlled by a variety of measurement sensors.

Abstract: The present invention provide a vertical nano-sized transistor using carbon nanotubes capable of achieving high-density integration, that is, tera-bit scale integration, and a manufacturing method thereof, wherein in the vertical nano-sized transistor using carbon nanotubes, holes having diameters of several nanometers are formed in an insulating layer and are spaced at intervals of several nanometers. Carbon nanotubes are vertically aligned in the nano-sized holes by chemical vapor deposition, electrophoresis or mechanical compression to be used as channels. A gate is formed in the vicinity of the carbon nanotubes using an ordinary semiconductor manufacturing method, and then a source and a drain are formed at lower and upper parts of each of the carbon nanotubes thereby fabricating the vertical nano-sized transistor having an electrically switching characteristic.

Abstract: A magneto-resistive random access memory includes a MOS transistor having a first gate and source and drain junctions on a substrate, a lower electrode connected to the source junction, a first magnetic layer on the lower electrode, a dielectric barrier layer including aluminum and hafnium on the first magnetic layer which, together with the first magnetic layer, form a potential well, a second magnetic layer on the dielectric barrier layer opposite the first magnetic layer, an upper electrode on the second magnetic layer, a second gate interposed between the first gate and the lower electrode to control the magnetic data of one of the first and second magnetic layers, and a bit line positioned orthogonal to the first gate and electrically connected to the upper electrode. Improved characteristics of the barrier layer increase a magnetic resistance ratio and improve data storage capacity of the magneto-resistive random access memory.

Abstract: An apparatus for supplying chemicals in a chemical mechanical polishing (CMP) process includes a plurality of chemical solution supply sources for supplying different chemical solutions in a pump-less manner by using a pressure applied at the chemical solution supply sources, each supply source having an associated feed line, re-circulating line, and means for measuring and controlling flow rates of the chemical solutions supplied through the feed lines. The chemical solutions are delivered via a plurality of delivery lines to a mixer, thereby providing a mixed chemical solution to a chemical injection part of a polishing apparatus. Each means for measuring and controlling flow rates is mounted in the feed lines.

Abstract: A method of measuring a concentration of a material includes irradiating an infrared light onto a substrate having a layer including a first material and dopants, wherein the infrared light is partially absorbed by and partially transmitted through the substrate including the layer. Intensities of the infrared light absorbed in the first material and the dopants are computed according to light wave numbers by utilizing a difference between intensities of the infrared light before and after transmitting the substrate and layer and by utilizing a difference between intensities of the infrared light absorbed in the substrate and layer and absorbed in only the substrate. Concentrations of the dopants are obtained by utilizing a ratio of light wave number regions corresponding to predetermined intensities of infrared light absorbed in the dopants relative to light wave number regions corresponding to the predetermined intensity of infrared light absorbed in the first material.

Abstract: A plasma enhanced chemical vapor deposition apparatus and a method of forming a nitride layer using the same, wherein the plasma enhanced CVD apparatus includes a process chamber including an upper chamber with a dome shape, a lower chamber, and an insulator therebetween, a gas distributing ring, a susceptor for supporting a wafer and heating the process chamber, a plasma compensation ring surrounding the susceptor, a vacuum pump and an electric power source connected to the process chamber. The gas distributing ring has a plurality of upwardly inclined nozzles, allowing upward distribution of reactive gases. The method of forming a nitride layer includes forming a protective film on inner walls of a process chamber, the protective film having at least two layers of differeing dielectric constant, and sequentially supplying reactive gases to the process chamber. A nitride layer formed thereby has low hydrogen content, good density and oxidation resistance.

Abstract: An electron beam lithography apparatus, which uses a patterned emitter, includes a pyroelectric plate emitter that emits electrons using a patterned metal thin layer formed on the pyroelectric plate as a mask. When the emitter is heated, electrons are emitted from portions of the emitter covered with a patterned dielectric layer, and not from portions of the emitter covered with a patterned metal thin layer, and a pattern of the emitter is thereby projected onto a substrate. To prevent dispersion of emitted electron beams, the electron beams may be controlled by a permanent magnet, an electro-magnet, or a deflector unit. A one-to-one or x-to-one projection of a desired pattern on the substrate is thereby obtained.

Abstract: A blue electroluminescent compound and an organic electroluminescent device using the blue electroluminescent compound, which includes a 9,10-diphenyl anthracene unit in its backbone and has alkoxy groups and substituted or unsubstituted amino group introduced to the 2 and 5 positions on the phenyl group in the diphenyl anthracene unit.

Abstract: Provided is an antenna apparatus including an antenna for receiving electromagnetic radiation from an object to be measured; and a condensing element, which is constructed to surround the antenna, which is located at a center of the condensing element, wherein the condensing element reflects and condenses the electromagnetic radiation toward the antenna. The antenna apparatus according to the present invention improves the gain and electromagnetic reception efficiency of the antenna and effectively reduces interference by external unwanted noise.

Abstract: A method for forming a ternary thin film using an atomic layer deposition process includes supplying a first and a second reactive material to a chamber containing a wafer, the first and second reactive materials being adsorbing on a surface of the wafer, supplying a first gas to the chamber to purge the first and second reactive materials that remain unreacted, supplying a third reactive material to the chamber to cause a reaction between the first and second reactive materials and the third reactive material to form a thin film monolayer, supplying a second gas to purge the third reactive material that remains unreacted and a byproduct, and repeating the above steps for forming the thin film monolayer a predetermined number of times to form a ternary thin film having a predetermined thickness on the wafer. Preferably, the ternary thin film is a SiBN film.

Abstract: A memory merged logic (MML) semiconductor device of NMOS and PMOS dual gate structure including embedded memory of a self-aligned structure and a method of manufacturing the same, wherein in the MML semiconductor device, the memory area including n-type metal oxide semiconductor (NMOS) and p-type metal oxide semiconductor (PMOS) are integrated together, wherein the memory area includes a polycide gate electrode, a hard mask pattern comprised of nitride materials which is formed on the polycide gate electrode, a spacer comprised of nitride materials formed along the sidewall of the polycide gate electrode, and a self-aligned contact which is formed between the adjacent spacers and electrically connected with an impurity implantation region formed on a semiconductor substrate. The logic area includes salicided NMOS and PMOS gate electrodes and salicided source/drain regions, and the height of the polycide gate electrode is smaller than the height of the NMOS and PMOS gate electrodes.

Abstract: A single transistor type magnetic random access memory device and a method of operating and manufacturing the same, wherein the single transistor type magnetic random access memory device includes a substrate, first and second doped regions spaced apart from each other, a gate dielectric layer on a portion of the semiconductor substrate between the first and second doped regions, a magnetic tunnel junction on the gate dielectric layer, word lines on the magnetic tunnel junction extending in a first direction which is the same direction as the second doped region, bit lines connected to the first doped region in a second direction perpendicular to the first direction, and an insulating layer covering the gate dielectric layer, the magnetic tunnel junction, and the word lines. The single transistor type magnetic random access memory device has a simple circuit structure, has a prolonged lifetime and is easy to manufacture.

Abstract: The present invention relates to a capacitor of a semiconductor memory cell and a method of manufacturing the same wherein a capacitor includes a first insulation layer having a buried contact hole, formed on a semiconductor substrate, and a buried contact plug filling a portion of the buried contact hole. A diffusion barrier spacer is formed on an inner surface of the buried contact hole above the buried contact plug. A second insulation layer is formed, having a through hole larger than the buried contact hole, for exposing the diffusion barrier spacer and a top surface of the contact plug. A barrier layer is formed on the through hole and a lower electrode is formed on the barrier layer. A dielectric layer is formed on the lower electrode and an upper surface of the second insulation layer and an upper electrode is formed on the dielectric layer.

Abstract: A method of preparing nanosized spherical vanadium oxide particles, comprising preparing a vanadium ion-containing aqueous solution by dissolving a vanadium ion-containing material; adding at least one solvent selected from a non-protonic, polar organic solvent and a glycol solvent to the vanadium ion-containing aqueous solution and mixing the same; and aging the mixture.

Abstract: A method for forming a self-aligned contact hole includes forming a plurality of conductive structures on a semiconductor substrate, each conductive structure including a conductive film pattern and a protection pattern formed on the conductive film pattern, forming a first insulation film to fill a space between adjacent conductive structures, successively etching the first insulation film and the protection patterns until each of the protection patterns has an exposed level upper surface, forming a second insulation film on the resultant structure, and selectively etching portions of the second insulation film and the first insulation film using a photolithography process to form the self-aligned contact hole exposing a portion of the semiconductor substrate between adjacent conductive structures.

Abstract: The present invention discloses a method of manufacturing a semiconductor device having an upper capacitor electrode and a node resistor, including depositing a thin film at a first deposition rate on an edge portion of a wafer and at a second deposition rate on a central portion of the wafer to form the upper capacitor electrode and the node resistor, thereby improving step coverage of the upper capacitor electrode while simultaneously improving resistance distribution of the node resistor.

Abstract: A decision feedback equalizer and a method for updating tap coefficients of the decision feedback equalizer are provided. The decision feedback equalizer (DFE) includes a first equalizer for reducing channel interference noise in an input signal, a second equalizer for generating a feedback signal for reducing remaining interference noise, and an update controller for controlling the first and the second equalizers so as to freeze the second equalizer when the first equalizer is updated and to freeze the first equalizer when the second equalizer is updated. The tap coefficients of the feedforward equalizer and the feedback equalizer are alternately initialized. It then becomes possible to stably converge the levels of respective tap coefficients without diverging them and to reduce the power used for updating the tap coefficients in a steady state.