Abstract: Access points in wireless networks provide contention free access to stations through polling. Polling frames are transmitted to stations at polling intervals. Stations may transmit polling alignment requests to the access point to request a modification of the polling interval. Virtual polling is provided by publishing a virtual polling schedule. Stations respond to the virtual polling schedule without receiving polling frames. Polling intervals used during virtual polling may be modified in response to polling alignment requests from mobile stations.
Abstract: The effects of interference are mitigated in a wireless system by estimating spatial characteristics of an interfering signal, and using those characteristics in the formation of a spatial equalizer.
Type:
Grant
Filed:
May 26, 2005
Date of Patent:
March 23, 2010
Assignee:
Intel Corporation
Inventors:
William J. Chimitt, Sudhakar Kalluri, Keith Holt
Abstract: A gate-to-source voltage (Vgs) replication circuit includes a diode-connected NMOS transistor coupled to a current source to draw a drain-to-source current therethrough. The generated Vgs is imposed across a source-to-gate junction of a PMOS transistor. A second PMOS transistor is coupled in series with the first PMOS transistor such that the source-to-gate voltage (Vsg) of the second PMOS transistor replicates the Vgs of the NMOS circuit. The second PMOS transistor is coupled as a source follower to bias other NMOS transistors.
Abstract: A computing platform includes a wireless interface and other devices that may cause interference to the wireless interface. The other devices may change frequencies of operation or data rates to steer signal spectrum away from current wireless channels and reduce interference to the wireless interface.
Type:
Grant
Filed:
June 30, 2005
Date of Patent:
March 9, 2010
Assignee:
Intel Corporation
Inventors:
Xintian E. Lin, Qinghua Li, Lei Shao, Allen W. Bettner
Abstract: An integrated circuit communicates with memory devices. Data from the memory devices arrives at the integrated circuit with varying propagation delays. The integrated circuit detects the arrival of data from the memory devices, and stores the data in FIFOs. A FIFO drain signal is generated responsive to the detection of the data arrival.
Abstract: The effects of interference are mitigated in a wireless system through update noise variance estimates. Noise variance estimates may be update after the reception of a preamble in an OFDM receiver. Noise variance estimates may include averages of signal energy over multiple symbols in one OFDM tone and over multiple OFDM tones. A co-located wireless personal area network (WPAN) interface may signal its presence a wireless local area network (WLAN) interface, which may select a noise variance estimate algorithm based therein.
Type:
Grant
Filed:
December 20, 2004
Date of Patent:
January 26, 2010
Assignee:
Intel Corporation
Inventors:
Xintian E. Lin, Qinghua Li, Camille C. Chen
Abstract: A radio receiver measures a signal quality metric and modifies attributes of a local oscillator signal in response thereto. A digital signal processor may be used to determine a signal-to-noise-plus-distortion ratio (SNDR) of a baseband signal, and the overlap of two quadrature-related local oscillator signals may be modified.
Type:
Grant
Filed:
March 6, 2007
Date of Patent:
December 8, 2009
Assignee:
Intel Corporation
Inventors:
Stewart S. Taylor, Jing-Hong C Zhan, Brent Carlton
Abstract: A volatile or nonvolatile cache memory can cache mass storage device read data and write data. The cache memory may become inaccessible, and I/O operations may go directly to the mass storage device, bypassing the cache memory. A log of write operations may be maintained to update the cache memory when it becomes available.
Type:
Grant
Filed:
December 29, 2005
Date of Patent:
December 1, 2009
Assignee:
Intel Corporation
Inventors:
Sanjeev N. Trika, Michael K. Eschmann, Jeanna N. Matthews, Vasudevan Srinivasan
Abstract: A computer includes a wireless personal area network (WPAN) interface, a wireless local area network (WLAN) interface and a wireless wide area network (WWAN) interface. A device communicating with the wireless personal area network can command the computer to perform actions using the wireless local area network interface or wireless wide area network interface.
Type:
Grant
Filed:
March 31, 2004
Date of Patent:
September 15, 2009
Assignee:
Intel Corporation
Inventors:
Richard A. Forand, Riley W. Jackson, James P. Kardach
Abstract: An electronic transaction card communicates with an add-on slot of an intelligent electronic device. The add-on slot may be a memory card slot. The intelligent electronic device may be a mobile phone or other device with or without network connectivity. The electronic transaction card may have magnetic field producing circuitry compatible with magnetic card readers, smartcard circuitry, other point-of-sale interfaces, or any combination thereof.
Type:
Grant
Filed:
February 22, 2005
Date of Patent:
September 1, 2009
Assignee:
Tyfone, Inc.
Inventors:
Siva G. Narendra, Thomas N. Spitzer, Prabhakar Tadepalli
Abstract: Film bulk acoustic resonators (FBARS) have resonant frequencies that vary with manufacturing variations, but tend to be matched when in proximity on an integrated circuit die. FBAR resonant frequency is determined using a fractional-N synthesizer and comparing phase/frequency of an output signal from the fractional-N synthesizer to a reference. The reference may be derived from a low frequency crystal oscillator, an external signal source, or a communications signal.
Abstract: A data frame includes multiple data blocks that are block encoded in a forward error correction (FEC) scheme. When received data blocks are corrupted, encoded versions of the data blocks are stored, and retransmission of the corrupted data blocks is requested. Upon receiving retransmitted data blocks, the retransmitted encoded data blocks are combined with stored encoded data blocks prior to decoding.
Abstract: A multi-level cell memory device performs a read by providing a stepped voltage waveform on a wordline, and comparing cell currents to a substantially constant reference current. Prior to the application of the stepped voltage waveform, the wordline may share charge with another circuit node.
Type:
Grant
Filed:
December 28, 2005
Date of Patent:
June 23, 2009
Assignee:
Intel Corporation
Inventors:
Kerry D. Tedrow, Dung Nguyen, Bo Li, Rezaul Haque, Ahsanur Rahman, Saad P. Monasa, Matthew Goldman
Abstract: An amplifier circuit receives a phase modulated signal at an input node. The power supply terminal of the amplifier circuit is modulated in accordance with an amplitude envelope signal. The voltage on the power supply terminal is modulated using one or more linear regulators depending on the magnitude of the envelope signal.
Abstract: Feedback bandwidth may be reduced in a closed loop MIMO system by Householder transformations, vector quantization using codebooks, and down-sampling in the frequency domain. A column of a beamforming matrix is quantized using a codebook, a Householder reflection is performed on the beamforming matrix to reduce the dimensionality of the beamforming matrix, and the quantizing and performing of Householder reflection on the previously dimensionality reduced beamforming matrix is recursively repeated to obtain a further reduction of dimensionality of the beamforming matrix. These actions are performed for a subset of orthogonal frequency divisional multiplexing (OFDM) carriers, and quantized column vectors for the subset of OFDM carriers are transmitted.
Abstract: A voltage reference generator includes multiple closed loop voltage references. Each of the closed loop voltage references uses a flash cell with a variable threshold voltage and a feedback loop to trim a reference voltage. The voltage reference generator includes sample and hold capacitors in output stages to allow reference voltages to be refreshed during a standby mode of operation.
Abstract: A compound automatic gain control (AGC) circuit includes multiple AGC stages coupled with signal input nodes and signal output nodes in parallel. Each of the AGC stages has separate, individually controllable, control inputs. During gain back off, the AGC stages are backed off in sequence.