Abstract: A cyclic analog to digital converter (ADC) circuit operates to convert an analog input voltage into a digital output word. The ADC circuit includes an amplifier and capacitors configured as an integrator.

Abstract: An amplifier includes a Darlington transistor pair and a biasing network to increase bias currents in an input transistor.

Abstract: A translation look-aside buffer (TLB) has lockable entries. A number of entries to lock may be determined by counting unique page access instances during an active period of a process, determining a value of a page usage metric for the process, and comparing the value of the page usage metric to values of page usage metrics for other processes. The page usage metric may consider many different factors, including the amount of time a process is active, a frequency of invocation of the process, and a priority level of a process.

Abstract: Arrangements for automatic re-legging of transistors.

Abstract: A method and apparatus for converting skew in a received signal to a low frequency voltage. A signal is received at a destination node from an original signal from a source node. A unity time-voltage sawtooth ramp signal is created at the destination node. The amplitude of the unity time-voltage sawtooth ramp signal is a value in voltage proportional to a pulse width value of the original signal. The unity time-voltage sawtooth ramp signal starts just before the start of the received signal. A skew time is measured from the start of the unity time-voltage sawtooth ramp signal to a threshold level on an edge of the received signal. The measured skew time is correlated to a voltage level on the unity time-voltage sawtooth ramp. The measured skew time for each edge is converted into a pulse where the voltage level of each pulse being proportional to the measured skew.

Abstract: Compilation of a design description for a heterogeneous reconfigurable architecture is influenced by user-specified constraints.

Abstract: A row of floating-body single transistor memory cells is written to in two phases.

Abstract: A flash memory includes multi-level cells (MLC) that are programmed with a combination of coarse gate voltage steps and fine gate voltage steps. The multi-level cells include floating gate transistors that are programmed by modifying the threshold voltages of the floating gate transistors. Coarse gate voltage steps are used until the threshold voltage any of the transistors being programmed reaches a reference value, and fine steps are used thereafter.

Abstract: A transistor may operate as a sleep transistor or as a regulator.

Abstract: Arrangements (circuits, methods, systems) having self-measurement of input/output (I/O) specifications (e.g., input trip-point, output drive-level and pin leakage).

Abstract: A voltage controlled oscillator includes two gain stages to split the bias current and reduce phase noise.

Abstract: An integrated circuit die includes optical interconnect ports on a first side and electrical interconnect ports on a second side.

Abstract: An amplifier includes multiple gain ranges. The gain range can be set by electrically adding or removing load devices.

Abstract: Transistor bodies are biased to modify delay in clock buffers.

Abstract: A functional random instruction testing (FRIT) method is provided for testing complex devices.

Abstract: An amplifier includes multiple stages. Early stages of the multi-stage amplifier have low gain and preserve bandwidth.

Abstract: An amplifier includes multiple gain ranges. The gain range can be set by electrically adding or removing load devices.

Abstract: A frequency prescaler includes an asynchronous counter having a least significant stage clocked by an input signal, and a first true single phase clock flip-flop having an input stage with an embedded logic gate to decode a state of the asynchronous counter, configured to modify a modulus of the asynchronous counter.

Abstract: A technique for de-skewing second and third clocks with respect to a first clock includes receiving the first clock and generating a fourth clock from the first and second clocks. A fifth clock and the third clock are generated from the fourth clock, the fifth clock being substantially identical to the third clock. The second clock is then generated from the fifth clock. The fourth clock is generated by a first phase locked loop having the first and second clocks as its inputs and the second clock is generated by a second phase locked loop connected to a clock tree, the second phase locked loop having the fifth clock and the second clock as its inputs.

Abstract: A buffer circuit includes a resonant circuit. An output of the resonant buffer circuit transitions once for three transitions on an input.