Patents Represented by Attorney LeMoine Patent Services, PLLC
  • Patent number: 7339403
    Abstract: Clock error detections circuits can detect clock duty cycle error and/or quadrature phase error. During an evaluation phase, capacitors are charged. During an evaluation phase, the capacitors are unequally discharged based on the error. A positive feedback mechanism latches the result.
    Type: Grant
    Filed: June 29, 2006
    Date of Patent: March 4, 2008
    Assignee: Intel Corporation
    Inventors: Suwei Chen, Derek M. Conrow, Aaron K. Martin
  • Patent number: 7332964
    Abstract: A gain-step transconductor circuit operates with multiple gain values. The gain can be stepped from one gain value to another by selecting a different signal path between an input node and an output amplifier. The output amplifier may operate as a common source amplifier or a common gate amplifier.
    Type: Grant
    Filed: June 20, 2006
    Date of Patent: February 19, 2008
    Assignee: Intel Corporation
    Inventors: Jing-Hong C Zhan, Stewart S. Taylor
  • Patent number: 7334158
    Abstract: A processor may receive multiple signals corresponding to potential power faults. A control register in the processor may specify actions to be taken for each of the potential power faults.
    Type: Grant
    Filed: June 29, 2004
    Date of Patent: February 19, 2008
    Assignee: Intel Corporation
    Inventors: Vasudev J. Bibikar, Mark N. Fullerton
  • Patent number: 7315186
    Abstract: An equalized driver includes a voltage mode driver to drive data on a conductor and a current mode driver to provide equalization.
    Type: Grant
    Filed: June 6, 2005
    Date of Patent: January 1, 2008
    Assignee: Intel Corporation
    Inventors: Aaron K. Martin, William Dawson Kesling, Ravindran Mohanavelu
  • Patent number: 7313019
    Abstract: A step voltage generator includes multiple trainable voltage references. Each of the trimmable voltage references uses a flash cell with a variable threshold voltage and a feedback loop to trim a reference voltage. The threshold voltage of the flash cell can be programmed to affect the reference voltage.
    Type: Grant
    Filed: December 21, 2004
    Date of Patent: December 25, 2007
    Assignee: Intel Corporation
    Inventors: Hari Giduturi, Kerry D. Tedrow
  • Patent number: 7295827
    Abstract: A mobile station in an 802.11 wireless network dynamically adjusts a number of 802.11 beacon intervals to sleep based on a power savings level and a required wake-up time to receive packets from an access point. The power savings level is based on data traffic activity in a current period. The mobile station wakes up to receive a beacon, and if a beacon is not received, the mobile station sleeps for one additional beacon period.
    Type: Grant
    Filed: March 31, 2004
    Date of Patent: November 13, 2007
    Assignee: Intel Corporation
    Inventors: Jiewen Liu, Chih C. Tsien
  • Patent number: 7289568
    Abstract: A reconfigurable partial response encoder manages the emitted spectrum of a digital signal.
    Type: Grant
    Filed: November 19, 2003
    Date of Patent: October 30, 2007
    Assignee: Intel Corporation
    Inventors: Jeffrey C. Harp, Ernest T. Tsui
  • Patent number: 7272029
    Abstract: A sense amplifier transition encodes an output signal onto a bus such that the bus signal only transitions when a sensed bit line has a state different from the state of a previously sensed bit line. The sense amplifier includes a storage element that changes state when the bus signal is asserted. The output of the sense amplifier is conditionally inverted based on the state of the storage element.
    Type: Grant
    Filed: December 29, 2004
    Date of Patent: September 18, 2007
    Assignee: Intel Corporation
    Inventors: Steven K. Hsu, Ram K. Krishnamurthy, Mark A. Anders
  • Patent number: 7268569
    Abstract: A thermal feedback loop controls leakage current during burn-in of a circuit.
    Type: Grant
    Filed: December 28, 2004
    Date of Patent: September 11, 2007
    Assignee: Intel Corporation
    Inventors: Arman Vassighi, Ali Keshavarzi, Vivek K De
  • Patent number: 7242252
    Abstract: A biased transistor circuit utilizes a transistor that exhibits a change in threshold voltage as the drain-to-source voltage changes due to power supply voltage changes. A bias circuit senses the power supply voltage changes and modifies a gate bias voltage on the transistor to maintain a substantially constant drain bias current in the transistor.
    Type: Grant
    Filed: March 29, 2005
    Date of Patent: July 10, 2007
    Assignee: Intel Corporation
    Inventor: Stewart S. Taylor
  • Patent number: 7239254
    Abstract: A programmable multi-cycle signaling scheme provides synchronous communications over relatively large distances. An input digital data stream is de-multiplexed onto multiple conductors. The digital data stream is recreated at the far end of the conductors.
    Type: Grant
    Filed: March 31, 2006
    Date of Patent: July 3, 2007
    Assignee: Intel Corporation
    Inventors: Suryaprasad Kareenahalli, Zohar Bogin, Chee Hak Teh
  • Patent number: 7236748
    Abstract: Feedback bandwidth may be reduced in a closed loop MIMO system by representing a beamforming matrix using orthogonal generator matrices.
    Type: Grant
    Filed: September 30, 2004
    Date of Patent: June 26, 2007
    Assignee: Intel Corporation
    Inventors: Qinghua Li, Xintian E. Lin
  • Patent number: 7199743
    Abstract: A digital to analog converter (DAC) circuit operates least significant bit (LSB) first.
    Type: Grant
    Filed: December 29, 2004
    Date of Patent: April 3, 2007
    Assignee: Intel Corporation
    Inventors: Bryan K. Casper, Craig S. Petrie
  • Patent number: 7190931
    Abstract: A receiver is calibrated using a transmitter that can output a plurality of substantially constant amplitude signals.
    Type: Grant
    Filed: September 29, 2003
    Date of Patent: March 13, 2007
    Assignee: Intel Corporation
    Inventors: Bryan K. Casper, Aaron K. Martin, James E. Jaussi, Stephen R. Mooney
  • Patent number: 7176751
    Abstract: A trimmable voltage reference uses a flash cell with a variable threshold voltage and a feedback loop to trim a reference voltage. The threshold voltage of the flash cell can be programmed to affect the reference voltage.
    Type: Grant
    Filed: November 30, 2004
    Date of Patent: February 13, 2007
    Assignee: Intel Corporation
    Inventors: Hari Giduturi, Kerry D. Tedrow
  • Patent number: 7139199
    Abstract: A flash memory file system logically divides at least a portion of the flash memory into memory fragments and headers associated with the memory fragments. The flash memory file system also includes a transaction information structure in support of transacted operations. The transaction information structure includes fields to indicate whether a transaction has begun, whether commitment of the transaction has begun, and whether commitment of the transaction has been completed. File system operations may be rolled back if a transaction was interrupted.
    Type: Grant
    Filed: June 28, 2004
    Date of Patent: November 21, 2006
    Assignee: Intel Corporation
    Inventors: Sujaya Srinivasan, John C. Rudelic
  • Patent number: 7139951
    Abstract: A scan enabled storage device includes two storage elements and two input circuits. A data input circuit accepts a data signal, a clock signal, and a scan enable signal to inhibit the operation of the clock signal. A scan data input circuit accepts a scan data signal and a scan clock signal.
    Type: Grant
    Filed: June 29, 2004
    Date of Patent: November 21, 2006
    Assignee: Intel Corporation
    Inventor: Mark E. Schuelein
  • Patent number: 7123109
    Abstract: An oscillator circuit may be operated in a high power mode or a reduced power mode. The high power mode provides fast start-up of the oscillator circuit.
    Type: Grant
    Filed: December 15, 2004
    Date of Patent: October 17, 2006
    Assignee: Intel Corporation
    Inventors: Paul E. Stevenson, Jon E. Tourville, Nathan L. Pihlstrom
  • Patent number: 7120072
    Abstract: A two transistor memory cell includes a write transistor and a read transistor. When reading the memory cell, the read transistor is turned on, and a voltage develops on a read bit line.
    Type: Grant
    Filed: June 30, 2004
    Date of Patent: October 10, 2006
    Assignee: Intel Corporation
    Inventors: Yibin Ye, Dinesh Somasekhar, Muhammad M Khellah, Fabrice Paillet, Stephen H Tang, Ali Keshavarzi, Shih-Lien L Lu, Vivek K De
  • Patent number: 7102358
    Abstract: A transistor may have degraded characteristics because of an overvoltage condition. The degraded characteristics may be sensed to determine that the transistor has previously been subjected to an overvoltage condition.
    Type: Grant
    Filed: June 29, 2004
    Date of Patent: September 5, 2006
    Assignee: Intel Corporation
    Inventors: Ali Keshavarzi, Fabrice Paillet, Muhammad M Khellah, Dinesh Somasekhar, Yibin Ye, Stephen H Tang, Mohsen Alavi, Vivek K De