Abstract: Feedback bandwidth may be reduced in a closed loop MIMO system by factoring non essential information out of a beamforming matrix.

Abstract: Diffusion regions in a standard cell design are bridged across cell boundaries. Shallow trench isolation is reduced and nitride passivation thickness variation is reduced.

Abstract: A variable gain amplifier includes multiple gain stages. Each gain stage includes a gain transistor and a cascode transistor to form a cascode amplifier, and a current diversion transistor to divert current away from a cascode transistor to reduce gain in the stage. A control circuit is included to maintain substantially constant drain-to-source voltage and drain current in the gain transistor.

Abstract: A global clock recovery circuit and port circuit determine and combine static phase adjustment information and dynamic phase adjustment information for multiple data signals. Static phase adjustment information is determined for each of the multiple data signals, and dynamic phase adjustment information is determined in common for the multiple data signals.

Abstract: The duty cycle of a signal is modified by passing the signal through a plurality of inverting stages. The inverting stages each have bias circuitry to influence the input switching threshold of inverters. Multiple duty cycle modification circuits produce non-overlapping local oscillator signals in a system.

Abstract: A bias circuit includes multiple output legs. During a transition from a low power state to an operational state, multiple output legs are turned on to provide a bias voltage. After a suitable period, at least one of the multiple output legs is turned off.

Abstract: An amplifier circuit includes a low noise first stage and a wide dynamic range second stage. A feedback network coupled between the output of the second stage and the input of the first stage provides DC level shifting of the common mode input voltage. The common mode input voltage is shifted to a value that allows the output of the first stage to be compatible with the input of the second stage.

Abstract: A dual mesh interconnect network in a heterogeneous configurable circuit may be allocated between data communication and control communication.

Abstract: An access point in a wireless network receives link margin values from associated access points. The access point determines sensitivity values for the associated access points and determines a lower access point output power value from the sensitivity values. Beacons are transmitted at full power and remaining frames are transmitted at the lower access output power. A new access output power may be determined periodically, or when a station associates or disassociates.

Abstract: A parallel power amplifier includes a carrier amplifier and peak amplifier coupled to receive signals from a quadrature hybrid made up of slab inductors in an integrated circuit. The slab inductors may be on different layers in the integrated circuit and may have similar or dissimilar shapes.

Abstract: A data driver drives a data signal on a channel, and a current mode driver drives a varying current on the channel to reduce crosstalk.

Abstract: De-skew is performed on a nibble-by-nibble basis where a nibble is not limited to four bits.

Abstract: A hybrid power system includes a fuel cell and a secondary power source.

Abstract: Aggregate channel reciprocity in a wireless system is supported by calibrating transmitter/receiver pairs.

Abstract: A clock signal is deskewed relative to a data signal by sweeping a sampling point in time and sweeping an amplitude offset. Bit error measurements are made at each sampling point in time and compared. Bit error measurements may be made by comparing received data to predetermined data values. The predetermined data values may be sourced from a linear feedback shift register.

Abstract: Feedback bandwidth may be reduced in a closed loop MIMO system by Householder transformations and vector quantization using codebooks.

Abstract: An offset canceling buffer receives a reference voltage, and provides a modified reference voltage to a comparator. The modified reference voltage operates to cancel any comparator offset. The offset canceling buffer includes a digitally controllable current source to steer current in different paths based on comparator offset.

Abstract: A processor divides resources into secure resources and non-secure resources. Virtual-to-physical address translation page tables may be stored in either secure or non-secure memory.

Abstract: A transmitter may transmit using OFDM-MIMO or OFDM-SDMA depending on channel characteristics.

Abstract: A receiver estimates a channel parameter from a received signal. The channel parameter may a DC signal level, a carrier to interference ratio, a noise spectrum, or the like. The receiver performs channel equalization and produces estimated symbols. The estimated symbols are remodulated and the channel parameter is re-estimated. An initial estimation error is calculated as the difference between the two estimates. The estimated symbols are weighted using the initial estimation error, and channel decoding is performed. Estimated symbol weights may be reduced when the initial estimation error is above a threshold, and may be increased when the initial estimation error is below a threshold.