Abstract: An image recording device for forming a toner image on a photosensitive drum using an electrophotographic technique. The image recording device includes opposed metallic frames each having a notch for receiving and supporting an end of a metallic shaft of the photosensitive drum so that the photosensitive drum is supported between the metallic frames. A plate spring is located in the vicinity of one of the metallic frames such that the plate spring is forced to contact the photosensitive drum shaft when the photosensitive drum is supported between the metallic frames. The metallic frames have a fixed relation relative to a main frame of the image recording device. A power source is connected to the plate spring and the associated metallic frame is earthed. Thus, a current flows from the power source to the plate spring, the drum shaft and the associated metallic frame in turn when the photosensitive drum is supported on the metallic frames.

Abstract: A plate-making sheet in the form of a strip having two longer-sides and two shorter-sides includes a base sheet and an adhesive sheet laminated on the base sheet. The adhesive sheet has a label portion formed in the middle thereof for being printed with an image. The label portion is defined by a cutting line formed in the adhesive sheet. A plate-making sheet group includes a plurality of types of plate-making sheets having respective label portions different from each other, which are distinguished from each other in respect of color of at least one of the base sheet and the adhesive sheet. A printing apparatus for printing a stamp image on the label portion of the plate-making sheet comprises a printing mechanism for printing a stamp image on the label portion, a feed mechanism for feeding the plate-making sheet through the printing mechanism, and a sensor for detecting feeding of the plate-making sheet into the printing mechanism.

Abstract: The present invention provides a dielectric ceramic composition having a high dielectric constant and a high Q value in high frequency ranges, and also having a temperature coefficient .tau..sub.f of resonance frequency capable of being controlled stably in a small range. The dielectric ceramic composition contains at least lanthanide Ln, Al, Sr and Ti as metal elements, and has a composition for the metal elements, represented by the composition formula of aLn.sub.2 O.sub.x.bAl.sub.2 O.sub.3.cSrO.dTiO.sub.2, wherein a, b, c, d and x are confined as follows in mole ratio: 0.2194<a.ltoreq.0.4500, 0.2194<b.ltoreq.0.4500, 0.1000.ltoreq.c.ltoreq.0.4610, 0.1000.ltoreq.d.ltoreq.0.4610, 3.ltoreq.x.ltoreq.4, and a+b+c+d=1.

Abstract: The present invention provides a semiconductor integrated circuit device in which its internal node can be precharged at a high speed while suppressing current dissipation as in a conventional device by adding a circuit which assists charging when a power supply voltage begins to rise and a method for precharging. The semiconductor integrated circuit device includes a precharge circuit which comprises a first charge circuit, a second charge circuit which is higher in charging speed than the first charge circuit, a charged level detect circuit for detecting the charged level of the internal node when the first charge circuit is being driven, and a charged level stabilization circuit. The precharge circuit may further comprise a charged level control circuit.

Abstract: There are disclosed a self-crosslinked polymer solid electrolyte, a composite solid electrolyte, and a method of manufacturing the same. A high-energy ray is irradiated to a block-graft copolymer composed of a polymer block chain A represented by formula I and a polymer block chain B represented by formula III in order to crosslink the entire the system. A nonaqueous electrolytic solution is then added to the block-graft polymer to obtain a self-crosslinked polymer solid electrolyte. The self-crosslinked polymer solid electrolyte and an electrically insulating material are combined to obtain a composite solid electrolyte.

Abstract: A plasma display substrate comprising a rear plate and a plurality of partitions for forming display cells between every two adjacent partitions on one of the surfaces of the rear plate, wherein the partitions are molded independently of the rear plate with the mixture of ceramic or glass powder and a binder inclusive of organic additives and solvents are formed in a desired shape and a desired disposition on one of the surfaces of the rear plate made of ceramics or glass, and integrally joined to the rear plate. According to the substrate, the display cells have improved dimensional accuracy, particularly, the partitions having highly accurate flat side surfaces with no deformation and having a predetermined height can be formed easily. This disclosure also provides a method of producing the same.

Abstract: A CMOS integrated circuit device enabling accurate inspection of its static power source current includes: a CMOS circuit having a p-channel MOS transistor and an n-channel MOS transistor; a first pad connected to the source of the p-channel MOS transistor; a second pad connected to the source of the n-channel MOS transistor; a p-type diffused region formed in an n-type substrate or n-well having formed the p-channel MOS transistor; an n-type diffused region formed in the p-type substrate or p-well having formed the n-channel MOS transistor; a third pad connected through the p-type diffused region to the n-type substrate or n-well having formed the p-channel MOS transistor; and a fourth pad connected through the n-type diffused region to the p-type substrate or p-well having formed the n-channel MOS transistor.

Abstract: To decrease the area of a chip, improve the manufacturing efficiency and decrease the cost in a semiconductor device such as a driver integrated circuit having a number of output pads, and an electronic circuit device such as electronic clock. There are disposed output pads superposed in two dimensions on driving transistors or logic circuits connected thereto, respectively. Further, not only aluminum interconnection but also bump electrodes or barrier metals are used for the interconnection of the semiconductor device. In a case where a semiconductor integrated circuit is electrically adhered on to a printed circuit board in a face down manner, a solder bump disposed on the semiconductor integrated circuit and the interconnection of the printed circuit board are directly connected to each other, thereby realizing the electrical connection. On this occasion, the bump electrode as the external connecting terminal of the semiconductor integrated circuit is laminated on the transistor.

Abstract: At least one of the row- and column-selection mechanisms, including row- and column decoders, respectively, of a DRAM has a core circuit array and a control circuit array adjacent to each other. The core circuit array has an m-number of core circuit units which are substantially equivalent to each other, and each of which consists of an n-number of core circuits forming the decoders, respectively. The control circuit array has an m-number of control circuit units which are substantially equivalent to each other, and are connected to the core circuit units by interconnection wiring lines, respectively. The core circuit units and the control circuit units are arranged in a first direction with first and second pitches, respectively, which differ from each other.

Abstract: A developing apparatus employing a three-pole stationary magnetic roller for use with a uni-component magnetic developer or toner. The apparatus includes a rotational sleeve which accommodates the stationary roller, a mixer disposed in a toner vessel for stirring the toner, and a toner layer thickness regulator disposed upstream in the sleeve rotation direction from the developing position at which the image on a photo-sensitive drum is developed. The magnetic roller has a developing pole located near the developing position, a blade-facing pole facing the toner layer thickness regulator, and a shield pole located downstream in the sleeve rotation direction from the developing position, where the blade-facing pole and the shield pole are of the opposite polarity to the developing pole. The blade-facing pole and the shield pole generate a repulsive magnetic field therebetween, where the toner that has been stirred in the vessel comes in contact with the sleeve.

Abstract: An internal power supply voltage generation circuit used for a semiconductor memory device is disclosed. The semiconductor integrated circuit device includes a memory unit for storing data, and an internal power supply voltage generation unit for generating an internal power supply voltage VINT from an external power supply voltage VCC. The internal power supply voltage generation unit has a standby internal power supply voltage generation circuit and an activation internal power supply voltage generation circuit. The activation internal power supply voltage generation circuit is controlled by a control circuit. When a plurality of banks are set in the memory unit, the control circuit activates the activation internal power supply voltage generation circuit while at least one bank is active.

Abstract: An output circuit which outputs a data signal from an output terminal after setting the output terminal to a potential intermediate between a power supply line potential and a ground line potential. The output circuit includes an output drive configured of first and second transistors. The first transistor has a first control terminal to which is input a first control signal. The second transistor has a second control terminal to which is input a second control signal. It further includes a setting member which controls the first and second control signals to set the first and second transistors to the off state. It further includes a shorting member which shorts one of the first and second control terminals and the output terminal. Moreover, before the data signal is output, the transistors are set to the off state by the setting member, after which shorting is carried out according to the potential of the output terminal, and the output terminal is set to an intermediate potential.

Abstract: A combination weighing apparatus for performing a combination weighing of a plurality of articles to be weighed includes a plurality of containers Tb each bearing an information storage medium 1 on or from which product information including a weight value of the article to be weighed M2 is recorded or read-out, respectively, a write-in device 15 for writing the product information in the information storage medium 1, a read-out device 16 for reading the product information from the information storage medium 1, and a calculating device 4 for combining respective weight values of the articles to be weighed M2 which have been read out and for selecting a combination having a weight equal or approximating to a target value within a predetermined weight allowance. This combination weighing apparatus is effective to accomplish an easy and accurate combination calculation even though the order of transport of the articles to be weighed M2 changes.

Abstract: A synchronous DRAM has cell arrays arranged in a matrix, divided into banks accessed asynchronously, and n bit I/O buses for transferring data among the cell arrays. In the DRAM, the banks are divided into m blocks, the n-bit I/O buses located between adjacent banks are used for time sharing between adjacent banks in common, the n bit I/O buses, used for time sharing between adjacent banks in common, are grouped into n/m-bit I/O buses, every n/m bits for each block of m blocks of bank, and in each block in each bank, data input/output are carried out between the n/m-bit I/O buses and data bus lines in each block. A synchronous DRAM includes first and second internal clock systems for controlling a burst data transfer in which a string of burst data being transferred in synchronism with an external clock signal, when one of the internal clock systems is driven, the burst data transfer is commenced immediately by the selected internal clock system.

Abstract: A demodulating circuit demodulates a received signal, and outputs patterns of demodulated data and reliability information bits indicating correctness of the demodulated data. These are supplied to first and second shift registers (4 and 5), respectively. When the number of reliability information bits of Level 1 in the second shift register is a predetermined value or less, a shift operation is repeated a plurality of times. When a reliability information bit of Level 1 is outputted, an error correction control circuit (7) successively outputs all possible bit patterns of the demodulated data An EXOR gate (10) generates all possible patterns of demodulated data An error correcting circuit (11) carries out error correction for all the patterns. When the number is larger than the predetermined value, the error correction is carried out only for the demodulated data supplied from the demodulating circuit in a conventional manner.

Abstract: A semiconductor memory device includes bit lines and word lines arranged lengthwise and breadthwise, memory cells 1 capable of reading out and writing in, MOS transistors Q1 and Q2 for pre-charge, MOS transistors Q3 for short-circuiting, and transistors Q4 and Q5 for setting voltage level. The bit lines are provided two pieces at each bit. Between the MOS transistors Q1, Q2 for pre-charge and the bit lines driving power supply terminal Vcc, three pieces of the fuses F1-F3 are connected at each column. When the leak defect occurs to the bit lines, all of the fuses F1-F3 connected to the bit lines are cut. Further, a semiconductor memory device includes a plurality of section regions, a redundancy circuit RD1 which replaces a defective cell at each section region, a redundancy circuit RD2 which replaces the defective cell at each row address. The section regions are provided at each address in the column direction. In each section region, cell ground power supply lines Vss are formed circularly.