Abstract: An embodiment of the instant invention is a method of making a semiconductor device situated within a package with conductive leads extending from the package, the method comprising the steps of: testing a plurality of the semiconductor devices so as to determine defective devices; and marking the defective devices with a polymer marker able to withstand temperatures in excess of 200 C., acids with a pH of less than 2, and basic solutions with a pH of greater than 11. Preferably, the polymer marker is comprised of a surfactant, a solvent, a polymer backbone, and a dye, and may additionally include an adhesion promoter. The surfactant is, preferably, comprised of: SVC-15, isopropanol, and any combination thereof. The solvent is, preferably, comprised of a substance consisting of: ENSOLV, bromopropane, chloropropane, and C.sub.n H.sub.2n+1 X (where X is a halogen and n is between 3 and 5), and any combination thereof.

Abstract: A gate electrode of a MOS transistor wherein gate oxide 12 is placed over substrate 10. Boron-doped polysilicon gate electrode 14 is placed over gate oxide 12. Optionally, drain extender implants may be added to substrate 10. Low-temperature-deposited nitride layer 18 is placed over gate electrode 14 and gate oxide 12. The structure then undergoes a sidewall spacer etch to form sidewall spacers 20.

Abstract: An integrated circuit package (30) having first and second layers (76, 78), a plurality of routing pads (82) being integral with the first layer (76), a plurality of upper and lower conduits (18, 118), respectively, disposed on the upper and lower surfaces (92, 94) of the first layer (76), at least one of the upper conduits (18) electrically connected to at least one of the lower conduits (118), a plurality of pads (100) disposed on the second layer (78), vias (84) that electrically connect the pads (100) to the lower conduits (118) and a chip (50) adhered to the second layer (78) having bonding pads (120) at least one of which is electrically connected to at least one of the routing pads (82), is disclosed.

Abstract: A ball grid array package (10) is provided that includes a heat spreader (14), a stiffener (13), a substrate (16), and a die or chip (12). The stiffener (13) is mounted to the heat spreader (14) and has a cavity formed therein. The stiffener (13) may serve as either a ground plane or a power plane of ball grid array package (10), depending on the desired implementation. The substrate (16) includes a signal plane (30) and a power bus (28) on a first surface and has a cavity formed therein. The substrate (16) is mounted to the stiffener (13) through a second surface. The substrate (16) further having at least one hole formed from the first surface to the second surface and a plurality of solder balls, similar to solder ball (20), to provide an external connection to the ball grid array package (10).

Abstract: A method to improve the texture of titanium and aluminum to reduce electromigration by controlling the deposition conditions and the texture of the substrates. Aluminum films can develop strong <111> texture, when titanium is used underneath aluminum. However, to prevent the interaction between aluminum and titanium, a layer of TiN or other barrier is necessary. Fortunately, TiN has a similar atom arrangement on the <111> plane as that of aluminum <111> and titanium <002>. Therefore, by controlling the orientation of titanium using a pre-sputter argon etch and low titanium deposition temperature, the texture of titanium can be transferred to TiN, and subsequently to aluminum.

Abstract: A structure and method to direct the via 270 etch to the top of the interconnect 210, by using a sidewall layer 240, preferably TiN, and thus preventing the etching down the side of the interconnect 210 and exposure of materials residing between the interconnects 210.

Abstract: A system (270, 370) for connecting a semiconductor chip (22, 322) to a leadframe (12), the system (270, 370) includes a three-dimensional leadframe (12) and a bonding support mechanism (202, 302, 402). The leadframe (12) may include a first lead (32, 132, 332, 432) having a first base portion (144), a first lead tip (42, 142, 342, 442), and a first longitudinal axis (305); a second lead (30, 130, 330, 430) having a second base portion (140, 321), a second lead tip (36, 136, 336, 436), and a second longitudinal axis. The first lead (32, 132, 332, 432) and second lead (30, 130, 330, 430) formed substantially adjacent to each other, and the second lead (30, 130, 330, 430) having a stepped portion (38, 138, 338, 438) such that the lead tips (42, 142, 342, 442, 36, 136, 336, 436) of the first lead (132, 332, 432) and second lead (130, 330, 430) are separated in a Z-direction (52) and in a Y-direction (52).

Abstract: The invention provides a process for evaluating a substrate, such as a wafer of semiconductive material having a semiconductor die at least partially formed thereon, as to the condition of an overlying film, such as an overlying film of photoresist that is applied to the semiconductor die prior to metal etching and ion implantation. The condition of the film is evaluated by exposing at least a portion of the substrate to electromagnetic radiation and evaluating the wave profile of the reflected beam.In instances where it is desirable to evaluate the substrate for the presence or absence or photoresist, ultraviolet, or near ultraviolet light having a wavelength of about 240-650 nm can be used, as such wavelengths are strongly absorbed by photoresist. In contrast, areas of the substrate that are not covered by photoresist will not significantly absorb ultraviolet or near ultraviolet radiation.

Abstract: A device and method of making the device for regulating electromagnetic radiations in a predetermined frequency range, which comprises a substrate and a coating mixture on a surface of the substrate. The coating mixture is provided by mixing together: (a) a plurality of flakes of a magnetic or ferrite material having substantial length and width dimensions relative to their thickness, the thickness of substantially all of the flakes being less than the skin depth of all frequencies in the predetermined frequency range, (b) at least one surfactant, (c)) a vaporizable electrically insulating material and (d) a solvent. The mixture is sprayed onto the surface of the substrate, either with or without a magnetic field at the surface, and the solvent is removed to retain the flakes on the substrate spaced from each other by the electrically insulating material and disposed substantially parallel to the portion of the plane of the surface thereunder.

Abstract: A method of fabricating an oxidation barrier for a thin film is provided. The method may include forming a thin film (10) outwardly from a semiconductor substrate (12) and separated from the semiconductor substrate (12) by a primary insulator layer (14). A reactive layer (16) may be formed in-situ adjacent to the thin film (10). An oxidation barrier (20) may be formed by a chemical reaction between the thin film (10) and the reactive layer (16). The oxidation barrier (20) may comprise a silicide alloy that operates to reduce oxidation of the thin film (10).

Abstract: One embodiment of the instant invention is a process chamber for heating a semiconductor wafer, the process chamber comprising: heating elements (elements 104 of FIG. 2a) for providing heating energy; means for holding (means 112 of FIG. 2a) the semiconductor wafer; and shutters situated between the heating elements and the means for holding the semiconductor wafer, the shutters (shutters 108 of FIGS. 2a and 2b and shutters of FIGS. 2c and 2d for blocking the heating energy from getting to the semiconductor wafer when the shutters are in a closed position and for directing the heating energy to the semiconductor wafer when in an open position.

Abstract: An integrated circuit package (30) comprising a substrate (70) having an opening (86) and first and second surfaces (92, 94), a plurality of routing strips (82) being integral with the substrate (70) and extending to opening (86), a plurality of pads (100) disposed on the first surface (92) and electrically connected with at least one of the routing strips (82), a chip (50) having bonding pads (120) is adhered to the second surface (84) of the substrate (70) and is of substantially the same outline as substrate (70), wire bonding (80) electrically connecting at least one bonding pad (120) to at least one of the routing strips (82) and potting material (90) filling the opening (86) is disclosed.

Abstract: An embodiment of the instant invention is a method of forming a nano-rugged silicon-containing layer, the method comprising the steps of: providing a first silicon-containing layer (steps 202 or 802); providing a patterning layer over the first silicon-containing layer (steps 204 or 804); the patterning layer comprised of an amorphous substance; providing a second silicon-containing layer (steps 206 or 808) over the patterning layer; and wherein the patterning layer creates a nano-rugged texture in the second silicon-containing layer. Preferably, the first and second silicon-containing layers are comprised of polycrystalline silicon. In an alternative embodiment, the patterning layer is comprised of a material which has small holes such that the step of providing the second silicon-containing layer utilizes the first silicon-containing layer as a seed layer through the small holes so as to form the second silicon-containing layer.

Abstract: A novel Finite Impulse Response filter (FIR) Filter is provided which includes a plurality of multipliers (14-22), a plurality of multiplexers (24-32), and a plurality of sample and hold circuits (34-42). At least two of the sample and hold circuit output signals (1-5) may be multiplexed in a round robin fashion to at least two of the multipliers (14-22). The multipliers may receive as a second input, fixed tap coefficient signals (C.sub.1 -C.sub.5) for multiplication with the multiplexed sample and hold circuit output signals (1-5).

Abstract: A circuit and method for implementing a MOSFET gate driver. Two bipolar NPN transistors (Q1, Q2), constructed to achieve rail-to-rail swings when driving a capacitive load (23) by overlapping their respective emitter regions (13) over their contained contact regions (19) to prolong internal device saturation and resulting turn-off delays, alternately connect the gate drive terminal (31) to either a supply terminal (HVDC) or an output terminal (29). Predrive circuitry for these transistors comprises NMOS transistors (M9, M18, M12 and M13). The NPN transistors are supplemented by a CMOS inverter (PMOS transistor M6 and NMOS transistor M17). A PMOS transistor (M7) provides additional base drive for transistor Q1 when the gate drive node is approaching the supply node. A diode (D2) protects transistor Q1 against base-emitter avalanche and protects transistor M7 from excessive drain-to-source voltages.

Abstract: A novel Finite Impulse Response ("FIR") filter (10)" is provided with precise timing acquisition. A master/slave sample and hold architecture is employed. In this architecture, an input signal (VIN) is coupled to an input of a master sample and hold circuit (34). A plurality of slave sample and hold circuits (36-44) are coupled to the output of the master sample and hold circuit. The outputs of the slave sample and hold circuits (36-44) are multiplexed to a plurality of multipliers (14-22) in a round robin manner.

Abstract: An embodiment of the instant invention is a method of fabricating a semiconductor device which includes a dielectric layer situated between a conductive structure and a semiconductor substrate, the method comprising the steps of: forming the dielectric layer (layer 14) on the semiconductor substrate (substrate 12); forming the conductive structure (structure 18) on the dielectric layer; doping the conductive structure with boron; and doping the conductive structure with a dopant which inhibits the diffusion of boron. The semiconductor device may be a PMOS transistor or a capacitor. Preferably, the conductive structure is a gate structure. The dielectric layer is, preferably, comprised of a material selected from the group consisting of: an oxide, an oxide/oxide stack, an oxide/nitride stack, and an oxynitride. Preferably, the dopant which inhibits the diffusion of boron comprises at least one group III or group IV element.

Abstract: A method for maintaining the buffer capacity of a polishing slurry during chemical-mechanical wafer polishing, the method comprising circulating the polishing slurry in a chemical-mechanical wafer polishing apparatus, monitoring the pH of the polishing slurry, combining an agent into the polishing slurry to adjust the pH of the polishing slurry and maintaining the pH of the polishing slurry within a predetermined range, thereby maintaining the buffer capacity of the polishing slurry.

Abstract: A CVD process for Ti--Si--N or Ti--B--N films wherein a single feed gas (preferably TDMAT) serves as the source for titanium and nitrogen, and another feed gas is used as the source for silicon or boron. This avoids gas-phase particulate nucleation while providing good conformality. When the required thickness has been deposited, the silicon or boron feed gas continues to flow for some time after the titanium/nitrogen or titanium/boron source gas has been turned off. This results in a Ti--N film with a Si-rich or B-rich surface, which is conformal and has a low defect density. In a second embodiment, a single feed gas, such as TDMAT, is thermally decomposed to form a Ti--N layer. A post-deposition anneal is performed in a gas which supplies silicon or boron, incorporating these materials into the layer. The incorporation of silicon or boron into the layer minimizes the absorption of oxygen into the films, and therefore stabilizes the resulting films.

Abstract: One embodiment of the instant invention is a test structure (FIGS. 1, 7 and 8) for determining the effect of various process steps on a plurality of devices with regards to charge-induced damage, the test structure comprising: the plurality of devices (device 10 of FIG. 1 and devices of FIGS. 7 and 8), each of the devices includes a plurality of device levels and device structures; a plurality of antennas (antenna 11 of FIG. 1, antennas of FIGS. 7 and 8) for receiving charged particles emitted during a process step, each of the antennas connected to a corresponding portion of the plurality of devices and wherein the antenna and the corresponding portion of the plurality of devices has a perimeter ratio and an antenna ratio; and wherein the perimeter ratios and the antenna ratios are different for different portions of the plurality of antennas and their corresponding portion of the plurality of devices so that the effect of the various process steps with regards to charge-induced damage can be determined.